DAC0830/DAC0831/DAC0832 8-Bit MuP Compatible, Double ...


DAC0830/DAC0831/DAC0832 8-Bit MuP Compatible, Double ...

DAC0830DAC0831DAC0832 8-Bit mPCompatible Double-Buffered D to A ConvertersGeneral DescriptionThe DAC0830 is an advanced CMOSSi-Cr 8-bit multiplyingDAC designed to interface directly with the 8080 80488085 Z80 and other popular microprocessors A depositedsilicon-chromium R-2R resistor ladder network dividesthe reference current and provides the circuit with excellenttemperature tracking characteristics (005% of Full ScaleRange maximum linearity error over temperature) The circuituses CMOS current switches and control logic toachieve low power consumption and low output leakagecurrent errors Special circuitry provides TTL logic input voltagelevel compatibilityDouble buffering allows these DACs to output a voltage correspondingto one digital word while holding the next digitalword This permits the simultaneous updating of any numberof DACsThe DAC0830 series are the 8-bit members of a family ofmicroprocessor-compatible DACs (MICRO-DACTM) For applicationsdemanding higher resolution the DAC1000 series(10-bits) and the DAC1208 and DAC1230 (12-bits) are availablealternativesBI-FETTM and MICRO-DACTM are trademarks of National Semiconductor CorporationZ80 is a registered trademark of Zilog CorporationTypical ApplicationConnection Diagrams (Top Views)Dual-In-Line andSmall-Outline PackagesThis is necessary for the12-bit DAC1230 series topermit interchanging froman 8-bit to a 12-bit DACwith No PC board changesand no software changesSee applications sectionFeaturesFebruary 1995Y Double-buffered single-buffered or flow-through digitaldata inputsY Easy interchange and pin-compatible with 12-bitDAC1230 seriesY Direct interface to all popular microprocessorsY Linearity specified with zero and full scale adjust onlyNOT BEST STRAIGHT LINE FITY Works with g10V reference-full 4-quadrantmultiplicationY Can be used in the voltage switching modeY Logic inputs which meet TTL voltage level specs (14Vlogic threshold)Y Operates ‘‘STAND ALONE’’ (without mP) if desiredY Available in 20-pin small-outline or molded chip carrierpackageKey SpecificationsY Current settling time 1 msY Resolution 8 bitsY Linearity 8 9 or 10 bits(guaranteed over temp)Y Gain Tempco 00002% FSCY Low power dissipation 20 mWY Single power supply 5 to 15 VDCAllows easy upgrade to 12-bit DAC1230See application hintsTLH5608–1Molded Chip Carrier PackageDAC0830DAC0831DAC0832 8-Bit mP Compatible Double-Buffered D to A ConvertersTLH5608–22TLH5608–21C1995 National Semiconductor CorporationTLH5608RRD-B30M115Printed in U S A

Electrical Characteristics V REF e10000 V DC unless otherwise noted Boldface limits apply over temperatureT MIN sT A sT MAX For all other limits T A e25C (Continued)Symbol Parameter ConditionsVV CC e1575 V CC e12 V DC g5% VDC VCC e475 V CC e5V DCto 15 V DCSeeDC g5% g5% LimitNoteTested DesignTested Design UnitsTypTypLimit LimitLimit Limit(Note 12)(Note 12)(Note 5) (Note 6) (Note 5) (Note 6)AC CHARACTERISTICSt s Current SettingTimeV IL e0V V IH e5V10 10 mst W Write and XFER V IL e0V V IH e5V 11 100 250 375 600Pulse Width Min 9 320 320 900 900t DS Data Setup Time V IL e0V V IH e5V 9100 250 375 600Min 320 320 900 900t DH Data Hold Time V IL e0V V IH e5V 30 509Min 30 50t CS Control Setup Time V IL e0V V IH e5V 9110 250 600 900Min 320 320 1100 1100t CH Control Hold Time V IL e0V V IH e5V 009 0 10 0Min 0 0Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operatingthe device beyond its specified operating conditionsNote 2 All voltages are measured with respect to GND unless otherwise specifiedNote 3 The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX i JA and the ambient temperature T A The maximumallowable power dissipation at any temperature is P D e (T JMAX b T A )i JA or the number given in the Absolute Maximum Ratings whichever is lower For thisdevice T JMAX e 125C (plastic) or 150C (ceramic) and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80CW Forthe N package this number increases to 100CW and for the V package this number is 120CWNote 4 For current switching applications both I OUT1 and I OUT2 must go to ground or the ‘‘Virtual Ground’’ of an operational amplifier The linearity error isdegraded by approximately V OS d V REF For example if V REF e 10Vthena1mVoffset V OS onI OUT1 or I OUT2 will introduce an additional 001% linearity errorNote 5 Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)Note 6 Guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levelsNote 7 Guaranteed at V REF e g10 V DC and V REF e g1 V DC Note 8 The unit ‘‘FSR’’ stands for ‘‘Full Scale Range’’ ‘‘Linearity Error’’ and ‘‘Power Supply Rejection’’ specs are based on this unit to eliminate dependence on aparticular V REF value and to indicate the true performance of the part The ‘‘Linearity Error’’ specification of the DAC0830 is ‘‘005% of FSR (MAX)’’ Thisguarantees that after performing a zero and full scale adjustment (see Sections 25 and 26) the plot of the 256 analog voltage outputs will each be within005%cV REF of a straight line which passes through zero and full scaleNote 9 Boldface tested limits apply to the LJ and LCJ suffix parts onlyNote 10 A 100nA leakage current with R fb e20k and V REF e10V corresponds to a zero error of (100c10 b9c20c103 )c10010 which is 002% of FSNote 11 The entire write pulse must occur within the valid data interval for the specified t W t DS t DH and t S to applyNote 12 Typicals are at 25C and represent most likely parametric normNote 13 Human body model 100 pF discharged through a 15 kX resistorns4

Linearity Errora) End point test afterzero and fs adjTLH5608–3b) Best straight line c) Shifting fs adj to passbest straight line testDefinition of TermsResolution Resolution is directly related to the number ofswitches or bits within the DAC For example the DAC0830has 28 or 256 steps and therefore has 8-bit resolutionLinearity Error Linearity Error is the maximum deviationfrom a straight line passing through the endpoints of theDAC transfer characteristic It is measured after adjustingfor zero and full-scale Linearity error is a parameter intrinsicto the device and cannot be externally adjustedNational’s linearity ‘‘end point test’’ (a) and the ‘‘beststraight line’’ test (bc) used by other suppliers are illustratedabove The ‘‘end point test’’ greatly simplifies the adjustmentprocedure by eliminating the need for multiple iterationsof checking the linearity and then adjusting full scaleuntil the linearity is met The ‘‘end point test’’ guaranteesthat linearity is met after a single full scale adjust (One adjustmentvs multiple iterations of the adjustment) The ‘‘endpoint test’’ uses a standard zero and FS adjustment procedureand is a much more stringent test for DAC linearityPower Supply Sensitivity Power supply sensitivity is ameasure of the effect of power supply changes on the DACfull-scale outputSettling Time Settling time is the time required from a codetransition until the DAC output reaches within gLSB ofthe final output value Full-scale settling time requires a zeroto full-scale or full-scale to zero output changeFull-Scale Error Full scale error is a measure of the outputerror between an ideal DAC and the actual device outputIdeally for the DAC0830 series full-scale is V REF b1LSBFor V REF e10V and unipolar operation V FULL-SCALE e100000Vb39mVe9961V Full-scale error is adjustable tozeroDifferential Nonlinearity The difference between any twoconsecutive codes in the transfer curve from the theoretical1 LSB is differential nonlinearityMonotonic If the output of a DAC increases for increasingdigital input code then the DAC is monotonic An 8-bit DACwhich is monotonic to 8 bits simply means that increasingdigital input codes will produce an increasing analog outputFIGURE 1 DAC0830 Functional DiagramTLH5608–46

Typical Performance CharacteristicsDigital Input Thresholdvs TemperatureDigital Input Thresholdvs V CCGain and Linearity ErrorVariation vs TemperatureGain and Linearity ErrorVariation vs Supply Voltage Write Pulse Width Data Hold TimeDAC0830 Series Application HintsThese DAC’s are the industry’s first microprocessor compatibledouble-buffered 8-bit multiplying D to A convertersDouble-buffering allows the utmost application flexibilityfrom a digital control point of view This 20-pin device is alsopin for pin compatible (with one exception) with theDAC1230 a 12-bit MICRO-DAC In the event that a system’sanalog output resolution and accuracy must be upgradedsubstituting the DAC1230 can be easily accomplishedBy tying address bit A 0 to the ILE pin a two-byte mPwrite instruction (double precision) which automatically incrementsthe address for the second byte write (startingwith A 0 e‘‘1’’) can be used This allows either an 8-bit or the12-bit part to be used with no hardware or software changesFor the simplest 8-bit application this pin should be tiedto V CC (also see other uses in section 11)Analog signal control versatility is provided by a precision R-2R ladder network which allows full 4-quadrant multiplicationof a wide range bipolar reference voltage by an applieddigital word10 DIGITAL CONSIDERATIONSA most unique characteristic of these DAC’s is that the 8-bitdigital input byte is double-buffered This means that thedata must transfer through two independently controlled 8-bit latching registers before being applied to the R-2R laddernetwork to change the analog output The addition of asecond register allows two useful control features First anyDAC in a system can simultaneously hold the current DACdata in one register (DAC register) and the next data word inthe second register (input register) to allow fast updating ofthe DAC output on demand Second and probably moreimportant double-buffering allows any number of DAC’s in aTLH5608–5system to be updated to their new analog output levelssimultaneously via a common strobe signalThe timing requirements and logic level convention of theregister control signals have been designed to minimize oreliminate external interfacing logic when applied to mostpopular microprocessors and development systems It iseasy to think of these converters as 8-bit ‘‘write-only’’ memorylocations that provide an analog output quantity All inputsto these DAC’s meet TTL voltage level specs and canalso be driven directly with high voltage CMOS logic in nonmicroprocessorbased systems To prevent damage to thechip from static discharge all unused digital inputs shouldbe tied to V CC or ground If any of the digital inputs areinadvertantly left floating the DAC interprets the pin as alogic ‘‘1’’11 Double-Buffered OperationUpdating the analog output of these DAC’s in a double-bufferedmanner is basically a two step or double write operationIn a microprocessor system two unique system addressesmust be decoded one for the input latch controlledby the CS pin and a second for the DAC latch which iscontrolled by the XFER line If more than one DAC is beingdriven Figure 2 the CS line of each DAC would typically bedecoded individually but all of the converters could share acommon XFER address to allow simultaneous updating ofany number of DAC’s The timing for this operation isshown Figure 3It is important to note that the analog outputs that willchange after a simultaneous transfer are those from theDAC’s whose input register had been modified prior to theXFER command7

DAC0830 Series Application Hints (Continued)FIGURE 2 Controlling Mutiple DACsTIE TO LOGIC 1 IF NOT NEEDED (SEE SEC 11)FIGURE 3TLH5608–6The ILE pin is an active high chip select which can be decodedfrom the address bus as a qualifier for the normal CSsignal generated during a write operation This can be usedto provide a higher degree of decoding unique control signalsfor a particular DAC and thereby create a more efficientaddressing schemeAnother useful application of the ILE pin of each DAC in amultiple DAC system is to tie these inputs together and usethis as a control line that can effectively ‘‘freeze’’ the outputsof all the DAC’s at their present value Pulling this linelow latches the input register and prevents new data frombeing written to the DAC This can be particularly useful inmultiprocessing systems to allow a processor other than theone controlling the DAC’s to take over control of the databus and control lines If this second system were to use thesame addresses as those decoded for DAC control (but fora different purpose) the ILE function would prevent theDAC’s from being erroneously alteredIn a ‘‘Stand-Alone’’ system the control signals are generatedby discrete logic In this case double-buffering can becontrolled by simply taking CS and XFER to a logic ‘‘0’’ ILEto a logic ‘‘1’’ and pulling WR 1 low to load data to the inputlatch Pulling WR 2 low will then update the analog output Alogic ‘‘1’’ on either of these lines will prevent the changingof the analog output8

DAC0830 Series Application Hints (Continued)ILEeLOGIC ‘‘1’’ WR2 and XFER GROUNDEDFIGURE 4TLH5608–712 Single-Buffered OperationIn a microprocessor controlled system where maximumdata throughput to the DAC is of primary concern or whenonly one DAC of several needs to be updated at a time asingle-buffered configuration can be used One of the twointernal registers allows the data to flow through and theother register will serve as the data latchDigital signal feedthrough (see Section 15) is minimized ifthe input register is used as the data latch Timing for thismode is shown in Figure 4Single-buffering in a ‘‘stand-alone’’ system is achieved bystrobing WR 1 low to update the DAC with CS WR 2 andXFER grounded and ILE tied high13 Flow-Through OperationThough primarily designed to provide microprocessor interfacecompatibility the MICRO-DAC’s can easily be configuredto allow the analog output to continuously reflect thestate of an applied digital input This is most useful in applicationswhere the DAC is used in a continuous feedbackcontrol loop and is driven by a binary up-down counter or infunction generation circuits where a ROM is continuouslyproviding DAC dataSimply grounding CS WR 1 WR 2 and XFER and tying ILEhigh allows both internal registers to follow the applied digitalinputs (flow-through) and directly affect the DAC analogoutput14 Control Signal TimingWhen interfacing these MICRO-DAC to any microprocessorthere are two important time relationships that must be consideredto insure proper operation The first is the minimumWR strobe pulse width which is specified as 900 ns for allvalid operating conditions of supply voltage and ambienttemperature but typically a pulse width of only 180ns isadequate if V CC e15V DC A second consideration is thatthe guaranteed minimum data hold time of 50ns shouldbe met or erroneous data can be latched This hold time isdefined as the length of time data must be held valid on thedigital inputs after a qualified (via CS) WRstrobe makes alow to high transition to latch the applied dataIf the controlling device or system does not inherently meetthese timing specs the DAC can be treated as a slow memoryor peripheral and utilize a technique to extend the writestrobe A simple extension of the write time by adding await state can simultaneously hold the write strobe activeand data valid on the bus to satisfy the minimum WR pulsewidthIf this does not provide a sufficient data hold time atthe end of the write cycle a negative edge triggered oneshotcan be included between the system write strobe andthe WR pin of the DAC This is illustrated in Figure 5 for anexemplary system which provides a 250ns WR strobe timewith a data hold time of less than 10nsThe proper data set-up time prior to the latching edge (LO toHI transition) of the WR strobe is insured if the WR pulsewidthis within spec and the data is valid on the bus for theduration of the DAC WR strobe15 Digital Signal FeedthroughWhen data is latched in the internal registers but the digitalinputs are changing state a narrow spike of current mayflow out of the current output terminals This spike is causedby the rapid switching of internal logic gates that are respondingto the input changesThere are several recommendations to minimize this effectWhen latching data in the DAC always use the input registeras the latch Second reducing the V CC supply for theDAC from a15V to a5V offers a factor of 5 improvement inthe magnitude of the feedthrough but at the expense ofinternal logic switching speed Finally increasing C C (Figure8) to a value consistent with the actual circuit bandwidthrequirements can provide a substantial damping effect onany output spikes9

DAC0830 Series Application Hints (Continued)FIGURE 5 Accommodating a High Speed System20 ANALOG CONSIDERATIONSThe fundamental purpose of any D to A converter is to providean accurate analog output quantity which is representativeof the applied digital word In the case of the DAC0830the output I OUT1 is a current directly proportional to theproduct of the applied reference voltage and the digital input22 Basic Unipolar Output Voltageword For application versatility a second output I OUT2 isprovided as a current directly proportional to the complementof the digital input BasicallyI OUT1 e V REF InputcDigital 15 kX 256I OUT2 e V REFInputc255bDigital15 kX 256where the digital input is the decimal (base 10) equivalent ofthe applied 8-bit binary word (0 to 255) V REF is the voltageat pin 8 and 15 kX is the nominal value of the internal resistanceR of the R-2R ladder network (discussed in Section21)Several factors external to the DAC itself must be consideredto maintain analog accuracy and are covered in subsequentsections21 The Current Switching R-2R LadderThe analog circuitry Figure 6 consists of a silicon-chromium(SiCr or Si-chrome) thin film R-2R ladder which is depositedon the surface oxide of the monolithic chip As a resultthere are no parasitic diode problems with the ladder (asthere may be with diffused resistors) so the reference voltageV REF can range b10V to a10V even if V CC for thedevice is 5V DC The digital input code to the DAC simply controls the positionof the SPDT current switches and steers the availableladder current to either I OUT1 or I OUT2 as determined by thelogic input level (‘‘1’’ or ‘‘0’’) respectively as shown inTLH5608–8Figure 6 The MOS switches operate in the current modewith a small voltage drop across them and can thereforeswitch currents of either polarity This is the basis for the 4-quadrant multiplying feature of this DACTo maintain linearity of output current with changes in theapplied digital code it is important that the voltages at bothof the current output pins be as near ground potential(0V DC ) as possible With V REF ea10V every millivolt appearingat either I OUT1 or I OUT2 will cause a 001% linearityerror In most applications this output current is converted toa voltage by using an op amp as shown in Figure 7The inverting input of the op amp is a ‘‘virtual ground’’ createdby the feedback from its output through the internal 15kX resistor R fb All of the output current (determined by thedigital input and the reference voltage) will flow through R fbto the output of the amplifier Two-quadrant operation canbe obtained by reversing the polarity of V REF thus causingI OUT1 to flow into the DAC and be sourced from the outputof the amplifier The output voltage in either case is alwaysequal to I OUT1 cR fb and is the opposite polarity of the referencevoltageThe reference can be either a stable DC voltage source oran AC signal anywhere in the range from b10V to a10VThe DAC can be thought of as a digitally controlled attenuatorthe output voltage is always less than or equal to theapplied reference voltage The V REF terminal of the devicepresents a nominal impedance of 15 kX to ground to externalcircuitryAlways use the internal R fb resistor to create an output voltagesince this resistor matches (and tracks with temperature)the value of the resistors used to generate the outputcurrent (I OUT1 )10

DAC0830 Series Application Hints (Continued)FIGURE 6FIGURE 723 Op Amp ConsiderationsThe op amp used in Figure 7 should have offset voltagenulling capability (See Section 25)The selected op amp should have as low a value of inputbias current as possible The product of the bias currenttimes the feedback resistance creates an output voltage errorwhich can be significant in low reference voltage applicationsBI-FET op amps are highly recommended for usewith these DACs because of their very low input currentTransient response and settling time of the op amp are importantin fast data throughput applications The largest stabilityproblem is the feedback pole created by the feedbackresistance R fb and the output capacitance of the DACThis appears from the op amp output to the (b) input andincludes the stray capacitance at this node Addition of alead capacitance C C in Figure 8 greatly reduces overshootand ringing at the output for a step change in DAC outputcurrentFinally the output voltage swing of the amplifier must begreater than V REF to allow reaching the full scale outputvoltage Depending on the loading on the output of the amplifierand the available op amp supply voltages (only g12volts in many development systems) a reference voltageless than 10 volts may be necessary to obtain the full analogoutput voltage range24 Bipolar Output Voltage with a Fixed ReferenceThe addition of a second op amp to the previous circuitrycan be used to generate a bipolar output voltage from afixed reference voltage This in effect gives sign significanceto the MSB of the digital input word and allows twoquadrantmultiplication of the reference voltage The polarityof the reference can also be reversed to realize full 4-quadrantmultiplication gV REF c gDigital Codee gV OUT Thiscircuit is shown in Figure 9TLH5608–9This configuration features several improvements over existingcircuits for bipolar outputs with other multiplyingDACs Only the offset voltage of amplifier 1 has to be nulledto preserve linearity of the DAC The offset voltage error ofthe second op amp (although a constant output voltage error)has no effect on linearity It should be nulled only ifabsolute output accuracy is required Finally the values ofthe resistors around the second amplifier do not have tomatch the internal DAC resistors they need only to matchand temperature track each other A thin film 4-resistor networkavailable from Beckman Instruments Inc (part no694-3-R10K-D) is ideally suited for this application Theseresistors are matched to 01% and exhibit only 5 ppmCresistance tracking temperature coefficient Two of the fouravailable 10 kX resistors can be paralleled to form R inFigure 9 and the other two can be used independently asthe resistances labeled 2R25 Zero AdjustmentFor accurate conversions the input offset voltage of theoutput amplifier must always be nulled Amplifier offset errorscreate an overall degradation of DAC linearityThe fundamental purpose of zeroing is to make the voltageappearing at the DAC outputs as near 0V DC as possibleThis is accomplished for the typical DAC op amp connection(Figure 7) by shorting out R fb the amplifier feedbackresistor and adjusting the V OS nulling potentiometer of theop amp until the output reads zero volts This is done ofcourse with an applied digital code of all zeros if I OUT1 isdriving the op amp (all one’s for I OUT2 ) The short aroundR fb is then removed and the converter is zero adjusted11

DAC0830 Series Application Hints (Continued)t sOP Amp C C (O to Full Scale)LF356 22 pF 4 msLF351 22 pF 5 msLF357 10 pF 2 msFIGURE 824 kX RESISTOR ADDED FROMbINPUT TOGROUND TO INSURE STABILITYV OUT eV REF(DIGITAL CODEb128)1281 LSBe l V REFl128TLH5608–10Input CodeIDEAL V OUTMSB LSB aV REF bV REFTHESE RESISTORS ARE AVAILABLE FROM 1 1 1 1 1 1 1 1 V REF b1 LSB blV REFla1 LSBBECKMAN INSTRUMENTS INC AS THEIR1 1 0 0 0 0 0 0 V REF 2 blVPART NO 694-3-R10K-DREFl21 0 0 0 0 0 0 0 0 00 1 1 1 1 1 1 1 l b1 LSB a1 LSBV0 0 1 1 1 1 1 1 b REFlb1 l VLSB REFla1 LSB220 0 0 0 0 0 0 0 blV REFl alV REFlFIGURE 926 Full-Scale AdjustmentIn the case where the matching of R fb to the R value of theR-2R ladder (typically g02%) is insufficient for full-scaleaccuracy in a particular application the V REF voltage can beadjusted or an external resistor and potentiometer can beadded as shown in Figure 10 to provide a full-scale adjustmentThe temperature coefficients of the resistors used for thisadjustment are an important concern To prevent degradationof the gain error temperature coefficient by the externalresistors their temperature coefficients ideally would haveto match that of the internal DAC resistors which is a highlyimpractical constraint For the values shown in Figure 10 ifthe resistor and the potentiometer each had a temperaturecoefficient of g100 ppmC maximum the overall gain errortemperature coefficent would be degraded a maximum of00025%C for an adjustment pot setting of less than 3%of R fb 27 Using the DAC0830 in a Voltage SwitchingConfigurationThe R-2R ladder can also be operated as a voltage switchingnetwork In this mode the ladder is used in an invertedmanner from the standard current switching configurationThe reference voltage is connected to one of the currentoutput terminals (I OUT1 for true binary digital control I OUT2is for complementary binary) and the output voltage is takenfrom the normal V REF pin The converter output is now avoltage in the range from 0V to 255256 V REF as a functionof the applied digital code as shown in Figure 11TLH5608–11FIGURE 10 Adding Full-Scale Adjustment12

DAC0830 Series Application Hints (Continued)FIGURE 11 Voltage Mode SwitchingTLH5608–12This configuration offers several useful application advantagesSince the output is a voltage an external op amp isnot necessarily required but the output impedance of theDAC is fairly high (equal to the specified reference inputresistance of 10 kX to 20 kX) so an op amp may be usedfor buffering purposes Some of the advantages of thismode are illustrated in Figures 12 13 14 and 15There are two important things to keep in mind when usingthis DAC in the voltage switching mode The applied referencevoltage must be positive since there are internal parasiticdiodes from ground to the I OUT1 and I OUT2 terminalswhich would turn on if the applied reference went negativeThere is also a dependence of conversion linearity andgain error on the voltage difference between V CC and thevoltage applied to the normal current output terminals Thisis a result of the voltage drive requirements of the ladderswitches To ensure that all 8 switches turn on sufficiently(so as not to add significant resistance to any leg of theladder and thereby introduce additional linearity and gainerrors) it is recommended that the applied reference voltagebe kept less than a5V DC and V CC be at least 9V morepositive than V REF These restrictions ensure less than01% linearity and gain error change Figures 16 17 and 18characterize the effects of bringing V REF and V CC closertogether as well as typical temperature performance of thisvoltage switching configuration Voltage switching mode eliminates output signal inversion and therefore aneed for a negative power supply Zero code output voltage is limited by the low level output saturation voltageof the op amp The 2 kX pull-down resistor helps to reduce this voltage V OS of the op amp has no effect on DAC linearityFIGURE 12 Single Supply DAC V OUT e25V D128 b1 JTLH5608–13 Slewing and settling time for a full scale output change is 18 msFIGURE 13 Obtaining a Bipolar Output from a FixedReference with a Single Op Amp13

DAC0830 Series Application Hints (Continued)FIGURE 14 Bipolar Output with Increased Output Voltage Swing Only a single a15V supply required Non-interactive full-scale and zero code output adjustments V MAX and V MIN must be s a5VDC and t0VTLH5608–14 Incremental Output Stepe 1256 (V MAX bV MIN)V OUT e D256 (V MAX bV MIN)a 255256 V MINFIGURE 15 Single Supply DAC with Level Shift and Span-Adjustable OutputGain and Linearity ErrorVariation vs Supply VoltageGain and Linearity ErrorVariation vs Reference VoltageGain and Linearity ErrorVariation vs TemperatureFIGURE 16 FIGURE 17Note For these curves V REF is the voltage appliedto pin 11 (I OUT1 ) with pin 12 (I OUT2 )groundedFIGURE 18TLH5608–1514

DAC0830 Series Application Hints (Continued)28 Miscellaneous Application HintsThese converters are CMOS products and reasonable careshould be exercised in handling them to prevent catastrophicfailures due to static dischargeConversion accuracy is only as good as the applied referencevoltage so providing a stable source over time andtemperature changes is an important factor to considerA ‘‘good’’ ground is most desirable A single point grounddistribution technique for analog signals and supply returnskeeps other devices in a system from affecting the output ofthe DACsDuring power-up supply voltage sequencing the b15V (orb12V) supply of the op amp may appear first This willcause the output of the op amp to bias near the negativesupply potential No harm is done to the DAC however asthe on-chip 15 kX feedback resistor sufficiently limits thecurrent flow from I OUT1 when this lead is internally clampedto one diode drop below groundCareful circuit construction with minimization of lead lengthsaround the analog circuitry is a primary concern Good highfrequency supply decoupling will aid in preventing inadvertantnoise from appearing on the analog outputApplicationsDAC Controlled Amplifier (Volume Control)Overall noise reduction and reference stability is of particularconcern when using the higher accuracy versions theDAC0830 and DAC0831 or their advantages are wasted30 GENERAL APPLICATION IDEASThe connections for the control pins of the digital input registersare purposely omitted Any of the control formats discussedin Section 1 of the accompanying text will work withany of the circuits shown The method used depends on theoverall system provisions and requirementsThe digital input code is referred to as D and represents thedecimal equivalent value of the 8-bit binary input for exampleBinary InputPin 13 Pin 7 DMSB LSB Decimal Equivalent1 1 1 1 1 1 1 1 2551 0 0 0 0 0 0 0 1280 0 0 1 0 0 0 0 160 0 0 0 0 0 1 0 20 0 0 0 0 0 0 0 0Capacitance Multiplier V OUT e bV IN (256)D When De0 the amplifier will go open loop and the output will saturate Feedback impedance from the binput to the output varies from 15 kX to% as the input code changes from full-scale to zero C EQUIV eC 1 1a256 D J Maximum voltage across the equivalent capacitance islimited to V O MAX (op amp)1a 256D C 2 is used to improve settling time of op ampTLH5608–1615

Applications (Continued)Variable f O Variable Q O Constant BW Bandpass Filter f O0 KD256e2qR 1 C Q O e 0 KD (2R Q a R 1)256 R Q (K a 1) 3dbBW e R Q (K a 1)2qR 1 C(2R Q a R1 )TLH5608–17where C 1 e C 2 e C K e R 6R 5and R 1 e RofDACe15k H O e 1 for R IN e R 4 e R 1 Range of f O andQis16 to 1 for circuit shown Therange can be extended to 255 to 1 by replacing R 1 with asecond DAC0830 driven by the same digital input word Maximum f Oc Q product should be s200 kHzDAC Controlled Function Generator DAC controls the frequency of sine square and triangle outputsD f e256(20k)C for V OMAX e V 0MIN of square wave output and R 1 e 3R 2 255 to 1 linear frequency range oscillator stops with D e 0 Trim symmetry and wave-shape for minimum sine wave distortionTLH5608–1816

Applications (Continued)Two Terminal Floating 4 to 20 mA Current Loop ControllerTLH5608–19I OUT e V REF 1 aDR 1 256 R fb( 1aR 2R 3( DAC0830 linearly controls the current flow from the input terminal to theoutput terminal to be 4 mA (for De0) to 1994 mA (for De255) Circuit operates with a terminal voltage differential of 16V to 55V P 2 adjusts the magnitude of the output current and P 1 adjusts the zeroto full scale range of output current Digital inputs can be supplied from a processor using opto isolators oneach input or the DAC latches can flow-through (connect control lines topins 3 and 10 of the DAC) and the input data can be set by SPST toggleswitches to ground (pins 3 and 10)DAC Controlled Exponential Time Response Output responds exponentially to input changes and automatically stopswhen V OUT eV IN Output time constant is directly proportional to the DAC input code andcapacitor C Input voltage must be positive (See section 27)TLH5608–2017

Ordering InformationTemperature Range 0Ctoa70 b40Ctoa85C b55Ctoa125CNon005% FSR DAC0830LCN DAC0830LCM DAC0830LCV DAC0830LCJ DAC0830LJLinearity 01% FSR DAC0831LCN02% FSR DAC0832LCN DAC0832LCM DAC0832LCV DAC0832LCJ DAC0832LJPackage Outline N20AMolded DIP M20B Small Outline V20A Chip Carrier J20ACeramic DIPPhysical Dimensions inches (millimeters)Ceramic Dual-In-Line Package (J)Order Number DAC0830LCJDAC0830LJ DAC0832LJ or DAC0832LCJNS Package Number J20A18

Physical Dimensions inches (millimeters) (Continued)Molded Small Outline Package (M)Order Number DAC0830LCMor DAC0832LCMNS Package Number M20BMolded Dual-In-Line Package (N)Order Number DAC0830LCNDAC0831LCN or DAC0832LCNNS Package Number N20A19

DAC0830DAC0831DAC0832 8-Bit mP Compatible Double-Buffered D to A ConvertersPhysical Dimensions inches (millimeters) (Continued)LIFE SUPPORT POLICYMolded Chip Carrier (V)Order Number DAC0830LCVor DAC0832LCVNS Package Number V20ANATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONALSEMICONDUCTOR CORPORATION As used herein1 Life support devices or systems are devices or 2 A critical component is any component of a lifesystems which (a) are intended for surgical implant support device or system whose failure to perform caninto the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the lifefailure to perform when properly used in accordance support device or system or to affect its safety orwith instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injuryto the userNational Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd Japan Ltd1111 West Bardin Road Fax (a49) 0-180-530 85 86 13th Floor Straight Block Tel 81-043-299-2309Arlington TX 76017 Email cnjwge tevm2nsccom Ocean Centre 5 Canton Rd Fax 81-043-299-2408Tel 1(800) 272-9959 Deutsch Tel (a49) 0-180-530 85 85 Tsimshatsui KowloonFax 1(800) 737-7018 English Tel (a49) 0-180-532 78 32 Hong KongFranais Tel (a49) 0-180-532 93 58 Tel (852) 2737-1600Italiano Tel (a49) 0-180-534 16 80 Fax (852) 2736-9960National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

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