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ELEN 468 Advanced Logic Design (Spring? 2001) Lab #8 Timing

ELEN 468 Advanced Logic Design (Spring? 2001) Lab #8 Timing

ELEN 468 Advanced Logic Design (Spring? 2001) Lab #8 Timing

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Starting PrimeTime:Change to the new directory created above and type Primetime & . This opens thePrimeTime tool. At the bottom of the window, there is a small box (called the pt_shell)where you type all the commands.Getting Help:To get a basic summary of all the PrimeTime commands, enterPrimetime> helpUse the help –verbose command to get command syntax information. EnterPrimetime> help –verbose Use the man pages for detailed help for each command and variable. To access the manpages, enter man followed by the name of the command or variable.Reading the design:PrimeTime works on gate-level netlist files in any of the following formats:- Synopsys database files (.db)- Verilog netlist files- Electronic Data Interchange Format (EDIF) netlist files- VHDL netlist filesSo the verilog code has to be synthesized to gate-level netlist before using PrimeTime onthe design. To generate the gate-level netlist file:1. Open the design_analyzer & window.2. Analyze & Elaborate the design.3. The design has to be optimized using the tools->design optimization menu.4. At the end of optimization, select the top module (in the hierarchy) and save the file.For reading the design, enterPrimetime> read_verilog flip_flop.This command will read in the module flip_flop.

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