BSIM3v3.2.2 MOSFET Model - The University of Texas at Dallas

BSIM3v3.2.2 MOSFET ModelUsers’ ManualWeidong Liu, Xiaodong Jin, James Chen, Min-Chie Jeng,Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui,Jianhui Huang, Robert Tu, Ping K. Ko and Chenming HuDepartment of Electrical Engineering and Computer SciencesUniversity of California, Berkeley, CA 94720Copyright © 1999The Regents of the University of CaliforniaAll Rights Reserved

Developers:The BSIM3v3.2.2 MOSFET model is developed by• Prof. Chenming Hu, UC Berkeley• Dr. Weidong Liu, UC Berkeley• Mr. Xiaodong Jin, UC BerkeleyDevelopers of Previous Versions:• Dr. Mansun Chan, USTHK• Dr. Kai Chen, IBM• Dr. Yuhua Cheng, Rockwell• Dr. Jianhui Huang, Intel Corp.• Dr. Kelvin Hui, Lattice Semiconductor• Dr. James Chen, UC Berkeley• Dr. Min-Chie Jeng, Cadence Design Systems• Dr. Zhi-Hong Liu, BTA Technology Inc.• Dr. Robert Tu, AMD• Prof. Ping K. Ko, UST, Hong Kong• Prof. Chenming Hu, UC BerkeleyWeb Sites to Visit:BSIM web site: http://www-device.eecs.berkeley.edu/~bsim3Compact Model Council web site: http://www.eia.org/eig/CMCTechnical Support:Dr. Weidong Liu: liuwd@bsim.eecs.berkeley.edu

Table of ContentsCHAPTER 1: Introduction 1-11.1 General Information 1-11.1 Backward compatibility 1-21.2 Organization of This Manual 1-2CHAPTER 2: Physics-Based Derivation of I-V Model 2-12.1 Non-Uniform Doping and Small Channel Effects on Threshold Voltage 2-12.1.1 Vertical Non-Uniform Doping Effect 2-32.1.2 Lateral Non-Uniform Doping Effect 2-52.1.3 Short Channel Effect 2-72.1.4 Narrow Channel Effect 2-122.2 Mobility Model 2-152.3 Carrier Drift Velocity 2-172.4 Bulk Charge Effect 2-182.5 Strong Inversion Drain Current (Linear Regime) 2-192.5.1 Intrinsic Case (Rds=0) 2-192.5.2 Extrinsic Case (Rds>0) 2-212.6 Strong Inversion Current and Output Resistance (Saturation Regime) 2-222.6.1 Channel Length Modulation (CLM) 2-252.6.2 Drain-Induced Barrier Lowering (DIBL) 2-262.6.3 Current Expression without Substrate Current InducedBody Effect 2-272.6.4 Current Expression with Substrate Current InducedBody Effect 2-282.7 Subthreshold Drain Current 2-302.8 Effective Channel Length and Width 2-312.9 Poly Gate Depletion Effect 2-33CHAPTER 3: Unified I-V Model 3-13.1 Unified Channel Charge Density Expression 3-13.2 Unified Mobility Expression 3-6BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 1

3.3 Unified Linear Current Expression 3-73.3.1 Intrinsic case (Rds=0) 3-73.3.2 Extrinsic Case (Rds > 0) 3-93.4 Unified Vdsat Expression 3-93.4.1 Intrinsic case (Rds=0) 3-93.4.2 Extrinsic Case (Rds>0) 3-103.5 Unified Saturation Current Expression 3-113.6 Single Current Expression for All Operating Regimes of Vgs and Vds 3-123.7 Substrate Current 3-153.8 A Note on V bs 3-15CHAPTER 4: Capacitance Modeling 4-14.1 General Description of Capacitance Modeling 4-14.2 Geometry Definition for C-V Modeling 4-24.3 Methodology for Intrinsic Capacitance Modeling 4-44.3.1 Basic Formulation 4-44.3.2 Short Channel Model 4-74.3.3 Single Equation Formulation 4-94.4 Charge-Thickness Capacitance Model 4-144.5 Extrinsic Capacitance 4-194.5.1 Fringing Capacitance 4-194.5.2 Overlap Capacitance 4-19CHAPTER 5: Non-Quasi Static Model 5-15.1 Background Information 5-15.2 The NQS Model 5-15.3 Model Formulation 5-25.3.1 SPICE sub-circuit for NQS model 5-35.3.2 Relaxation time 5-45.3.3 Terminal charging current and charge partitioning 5-55.3.4 Derivation of nodal conductances 5-7BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2

CHAPTER 6: Parameter Extraction 6-16.1 Optimization strategy 6-16.2 Extraction Strategies 6-26.3 Extraction Procedure 6-26.3.1 Parameter Extraction Requirements 6-26.3.2 Optimization 6-46.3.3 Extraction Routine 6-66.4 Notes on Parameter Extraction 6-146.4.1 Parameters with Special Notes 6-146.4.2 Explanation of Notes 6-15CHAPTER 7: Benchmark Test Results 7-17.1 Benchmark Test Types 7-17.2 Benchmark Test Results 7-2CHAPTER 8: Noise Modeling 8-18.1 Flicker Noise 8-18.1.1 Parameters 8-18.1.2 Formulations 8-28.2 Channel Thermal Noise 8-48.3 Noise Model Flag 8-5CHAPTER 9: MOS Diode Modeling 9-19.1 Diode IV Model 9-19.1.1 Modeling the S/B Diode 9-19.1.2 Modeling the D/B Diode 9-39.2 MOS Diode Capacitance Model 9-59.2.1 S/B Junction Capacitance 9-59.2.2 D/B Junction Capacitance 9-79.2.3 Temperature Dependence of JunctionCapacitance 9-10BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 3

9.2.4 Junction Capacitance Parameters 9-11APPENDIX A: Parameter List A-1A.1 Model Control Parameters A-1A.2 DC Parameters A-1A.3 C-V Model Parameters A-6A.4 NQS Parameters A-8A.5 dW and dL Parameters A-9A.6 Temperature Parameters A-10A.7 Flicker Noise Model Parameters A-12A.8 Process Parameters A-13A.9 Geometry Range Parameters A-14A.10 Model Parameter Notes A-14APPENDIX B: Equation List B-1B.1 I-V Model B-1B.1.1 Threshold Voltage B-1B.1.2 Effective (Vgs-Vth) B-2B.1.3 Mobility B-3B.1.4 Drain Saturation Voltage B-4B.1.5 Effective Vds B-5B.1.6 Drain Current Expression B-5B.1.7 Substrate Current B-6B.1.8 Polysilicon Depletion Effect B-7B.1.9 Effective Channel Length and Width B-7B.1.10 Source/Drain Resistance B-8B.1.11 Temperature Effects B-8B.2 Capacitance Model Equations B-9B.2.1 Dimension Dependence B-9B.2.2 Overlap Capacitance B-10B.2.3 Instrinsic Charges B-12BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4

APPENDIX C: References C-1APPENDIX D: Model Parameter Binning D-1D.1 Model Control Parameters D-2D.2 DC Parameters D-2D.3 AC and Capacitance Parameters D-7D.4 NQS Parameters D-9D.5 dW and dL Parameters D-9D.6 Temperature Parameters D-11D.7 Flicker Noise Model Parameters D-12D.8 Process Parameters D-13D.9 Geometry Range Parameters D-14BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 5

6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

CHAPTER 1: Introduction1.1 General InformationBSIM3v3 is the latest industry-standard MOSFET model for deep-submicrondigital and analog circuit designs from the BSIM Group at the University ofCalifornia at Berkeley. BSIM3v3.2.2 is based on its predecessor, BSIM3v3.2, withthe following changes:• A bias-independent Vfb is used in the capacitance models, capMod=1 and 2 toeliminate small negative capacitance of C gs and C gd in the accumulationdepletionregions.• A version number checking is added; a warning message will be given if userspecifiedversion number is different from its default value of 3.2.2.• Known bugs are fixed.1.2 Organization of This ManualThis manual describes the BSIM3v3.2.2 model in the following manner:• Chapter 2 discusses the physical basis used to derive the I-V model.• Chapter 3 highlights a single-equation I-V model for all operating regimes.• Chapter 4 presents C-V modeling and focuses on the charge thickness model.• Chapter 5 describes in detail the restrutured NQS (Non-Quasi-Static) Model.• Chapter 6 discusses model parameter extraction.• Chapter 7 provides some benchmark test results to demonstrate the accuracyand performance of the model.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 1-1

Organization of This Manual• Chapter 8 presents the noise model.• Chapter 9 describes the MOS diode I-V and C-V models.• The Appendices list all model parameters, equations and references.1-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold VoltageFirst, if the gate voltage is greater than the threshold voltage, the inversion chargedensity is larger than the substrate doping concentration and MOSFET is operatingin the strong inversion region and drift current is dominant. Second, if the gatevoltage is smaller than V th , the inversion charge density is smaller than thesubstrate doping concentration. The transistor is considered to be operating in theweak inversion (or subthreshold) region. Diffusion current is now dominant [2].Lastly, if the gate voltage is very close to V th , the inversion charge density is closeto the doping concentration and the MOSFET is operating in the transition region.In such a case, diffusion and drift currents are both important.For MOSFET’s with long channel length/width and uniform substrate dopingconcentration, V th is given by [2]:Vth= V +Φ + γ Φ −V= V + γFBssbsTideal( Φ −V− Φ )(2.1.1)where V FB is the flat band voltage, V Tideal is the threshold voltage of the longchannel device at zero substrate bias, and γ is the body bias coefficient and is givenby:sbssεγ = 2 siqNaCox(2.1.2)where N a is the substrate doping concentration. The surface potential is given by:(2.1.3)ΦskBT= 2q⎛ Nln⎜⎝ nia⎞⎟⎠2-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold VoltageEquation (2.1.1) assumes that the channel is uniform and makes use of the onedimensional Poisson equation in the vertical direction of the channel. This modelis valid only when the substrate doping concentration is constant and the channellength is long. Under these conditions, the potential is uniform along the channel.Modifications have to be made when the substrate doping concentration is notuniform and/or when the channel length is short, narrow, or both.2.1.1 Vertical Non-Uniform Doping EffectThe substrate doping profile is not uniform in the vertical direction asshown in Figure 2-1.N chN subFigure 2-1. Actual substrate doping distribution and its approximation.The substrate doping concentration is usually higher near the Si/SiO 2interface (due to V th adjustment) than deep into the substrate. Thedistribution of impurity atoms inside the substrate is approximately a halfBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-3

Non-Uniform Doping and Small Channel Effects on Threshold Voltagegaussian distribution, as shown in Figure 2-1. This non-uniformity willmake γ in Eq. (2.1.2) a function of the substrate bias. If the depletionwidth is less than X t as shown in Figure 2-1, N a in Eq. (2.1.2) is equal toN ch ; otherwise it is equal to N sub .In order to take into account such non-uniform substrate doping profile, thefollowing V th model is proposed:( Φs−Vbs− Φs) K VbsVth= VTideal+ K1 −2(2.1.4)For a zero substrate bias, Eqs. (2.1.1) and (2.1.4) give the same result. K 1and K 2 can be determined by the criteria that V th and its derivative versusV bs should be the same at V bm , where V bm is the maximum substrate biasvoltage. Therefore, using equations (2.1.1) and (2.1.4), K 1 and K 2 [3] willbe given by the following:K= γ2− K212Φ−sV bm(2.1.5)K2( γ1− γ )( Φs− Vbx− Φs)Φs( Φs− Vbm− Φs) + Vbm=22(2.1.6)where γ 1 and γ 2 are body bias coefficients when the substrate dopingconcentration are equal to N ch and N sub , respectively:γ1=2qεNCsioxch(2.1.7)2-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltageγ2=2qεNCsioxsub(2.1.8)V bx is the body bias when the depletion width is equal to X t . Therefore, V bxsatisfies:(2.1.9)qNchX2εsi2t= Φs− VbxIf the devices are available, K 1 and K 2 can be determined experimentally. Ifthe devices are not available but the user knows the doping concentrationdistribution, the user can input the appropriate parameters to specifydoping concentration distribution (e.g. N ch , N sub and X t ). Then, K 1 and K 2can be calculated using equations (2.1.5) and (2.1.6).2.1.2 Lateral Non-Uniform Doping EffectFor some technologies, the doping concentration near the source/drain ishigher than that in the middle of the channel. This is referred to as lateralnon-uniform doping and is shown in Figure 2-2. As the channel lengthbecomes shorter, lateral non-uniform doping will cause V th to increase inmagnitude because the average doping concentration in the channel islarger. The average channel doping concentration can be calculated asfollows:BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-5

Non-Uniform Doping and Small Channel Effects on Threshold VoltageNeffN=≡ Naa( L−2L)⎛ ⋅ ⎜1+⎝xLNlx⎞⎟L ⎠+ Npocket ⋅2Lx⎛ 2L= N⎜a1+⎝ LxNpocket−N⋅Naa⎞⎠(2.1.10)Due to the lateral non-uniform doping effect, Eq. (2.1.4) becomes:Vth= Vth0⎛+ K ⎜1⎜⎝+ K11 +( Φ −V− Φ )NlxLeffs⎞−1⎟⎟⎠bsΦss− K V2bs(2.1.11)Eq. (2.1.11) can be derived by setting V bs = 0, and using K 1 ∝ (N eff ) 0.5 . Thefourth term in Eq. (2.1.11) is used to model the body bias dependence ofthe lateral non-uniform doping effect. This effect gets stronger at a lowerbody bias. Examination of Eq. (2.1.11) shows that the threshold voltagewill increase as channel length decreases [3].NpocketNpocketN(x)N aL xXL xFigure 2-2. Lateral doping profile is non-uniform.2-6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltage2.1.3 Short Channel EffectThe threshold voltage of a long channel device is independent of the channellength and the drain voltage. Its dependence on the body bias is given byEq. (2.1.4). However, as the channel length becomes shorter, the thresholdvoltage shows a greater dependence on the channel length and the drainvoltage. The dependence of the threshold voltage on the body bias becomesweaker as channel length becomes shorter, because the body bias has lesscontrol of the depletion region. The short-channel effect is included in theV th model as:Vth= Vth0⎛+ K ⎜1⎜⎝+ K11+( Φ −V− Φ )NlxLeffs⎞−1⎟⎟⎠bsΦss− ∆V− K Vth2bs(2.1.12)where ∆V th is the threshold voltage reduction due to the short channeleffect. Many models have been developed to calculate ∆V th . They usedeither numerical solutions [4], a two-dimensional charge sharing approach[5,6], or a simplified Poisson's equation in the depletion region [7-9]. Asimple, accurate, and physical model was developed by Z. H. Liu et al.[10]. This model was derived by solving the quasi 2D Poisson equationalong the channel. This quasi-2D model concluded that:thth( L) ( ( V − Φ ) V )∆V = θ 2 +bisds(2.1.13)where V bi is the built-in voltage of the PN junction between the source andthe substrate and is given byBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-7

Non-Uniform Doping and Small Channel Effects on Threshold VoltageVbiKBTNchNd= ln( )2q ni(2.1.14)where N d in is the source/drain doping concentration with a typical value ofaroundcm -3 . The expression θ th (L) is a short channel effectcoefficient, which has a strong dependence on the channel length and isgiven by:1×10 20θ th ( L) = [exp( − L 2l t ) + 2exp( −L l t )](2.1.15)l t is referred to as the characteristic length and is given byltsiToxXdep= ε εoxη(2.1.16)X dep is the depletion width in the substrate and is given byXdep=2εsi( Φ −V)sqNchbs(2.1.17)X dep is larger near the drain than in the middle of the channel due to thedrain voltage. X dep / η represents the average depletion width along thechannel.Based on the above discussion, the influences of drain/source chargesharing and DIBL effects onV th are described by (2.1.15). In order to makethe model fit different technologies, several parameters such as D vt0 , D vt2 ,2-8 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold VoltageDsub, Eta0 and Etab are introduced, and the following modes are used toaccount for charge sharing and DIBL effects separately.θ th( L) = Dvt 0[exp( − Dvt1L/ 2lt ) + 2exp( −Dvt1L/ lt)]∆Vth( L) = θ ( L)( V − Φ )thbis(2.1.18)(2.1.19)ltεsiToxXdep= ( 1 + Dvt2Vbs)εox(2.1.20)θ dibl( L) = [exp( − Dsub L/ 2lt 0) + 2exp( −Dsub L/ lt0)]∆V ( V ) = θ ( )( E 0 + EV)Vth ds dibl L ta tab bs ds(2.1.21)(2.1.22)where l t0 is calculated by Eq. (2.1.20) at zero body-bias. D vt1 is basicallyequal to 1/(η) 1/2 in Eq. (2.1.16). D vt2 is introduced to take care of thedependence of the doping concentration on substrate bias since the dopingconcentration is not uniform in the vertical direction of the channel. X dep iscalculated using the doping concentration in the channel (N ch ). D vt0 ,D vt1 ,D vt2 , Eta0, Etab and Dsub, which are determined experimentally, canimprove accuracy greatly. Even though Eqs. (2.1.18), (2.1.21) and (2.1.15)have different coefficients, they all still have the same functional forms.Thus the device physics represented by Eqs. (2.1.18), (2.1.21) and (2.1.15)are still the same.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-9

Non-Uniform Doping and Small Channel Effects on Threshold VoltageAs channel length L decreases, ∆V th will increase, and in turn V th willdecrease. If a MOSFET has a LDD structure, N d in Eq. (2.1.14) is thedoping concentration in the lightly doped region. V bi in a LDD-MOSFETwill be smaller as compared to conventional MOSFET’s; therefore thethreshold voltage reduction due to the short channel effect will be smallerin LDD-MOSFET’s.As the body bias becomes more negative, the depletion width will increaseas shown in Eq. (2.1.17). Hence ∆V th will increase due to the increase in l t .The term:VTideal+ K1 Φs−Vbs− K2Vbswill also increase as V bs becomes more negative (for NMOS). Therefore,the changes inVTideal+ K1 Φs−Vbs− K2Vbsand in ∆V th will compensate for each other and make V th less sensitive toV bs . This compensation is more significant as the channel length isshortened. Hence, the V th of short channel MOSFET’s is less sensitive tobody bias as compared to a long channel MOSFET. For the same reason,the DIBL effect and the channel length dependence of V th are stronger asV bs is made more negative. This was verified by experimental data shownin Figure 2-3 and Figure 2-4. Although Liu et al. found an accelerated V throll-off and non-linear drain voltage dependence [10] as the channelbecame very short, a linear dependence of V th on V ds is nevertheless a goodapproximation for circuit simulation as shown in Figure 2-4. This figureshows that Eq. (2.1.13) can fit the experimental data very well.2-10 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold VoltageFurthermore, Figure 2-5 shows how this V th model can fit various channellengths under various bias conditions.Figure 2-3. Threshold voltage versus the drain voltage at different body biases.Figure 2-4. Channel length dependence of threshold voltage.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-11

Non-Uniform Doping and Small Channel Effects on Threshold VoltageFigure 2-5. Threshold voltage versus channel length at different biases.2.1.4 Narrow Channel EffectThe actual depletion region in the channel is always larger than what isusually assumed under the one-dimensional analysis due to the existence offringing fields [2]. This effect becomes very substantial as the channelwidth decreases and the depletion region underneath the fringing fieldbecomes comparable to the "classical" depletion layer formed from thevertical field. The net result is an increase in V th . It is shown in [2] that thisincrease can be modeled as:(2.1.23)πqNaX2CWox2d maxTox= 3πWΦs2-12 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold VoltageThe right hand side of Eq. (2.1.23) represents the additional voltageincrease. This change in V th is modeled by Eq. (2.1.24a). This formulationincludes but is not limited to the inverse of channel width due to the factthat the overall narrow width effect is dependent on process (i.e. isolationtechnology) as well. Hence, parameters K 3 , K 3b , and W 0 are introduced asox( K3+ K3V ) ΦsbbsWeffT' + W0(2.1.24a)W eff ’ is the effective channel width (with no bias dependencies), whichwill be defined in Section 2.8. In addition, we must consider the narrowwidth effect for small channel lengths. To do this we introduce thefollowing:(2.1.24b)D''⎛WeffLeffWeffLeff⎞⎜exp( − DVT w ) + 2exp( −DVT w ) ⎟( Vbi− Φs)⎝2ltwltw⎠VT 0w1 1When all of the above considerations for non-uniform doping, short andnarrow channel effects on threshold voltage are considered, the finalcomplete V th expression implemented in SPICE is as follows:BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-13

Non-Uniform Doping and Small Channel Effects on Threshold VoltageVth= V+ K− D− Dth0ox1oxVT0wVT0+ K1ox⎛ ⎛⎜exp⎜ − D⎝ ⎝⎛ ⎛ − ⎜exp⎜ − D⎝ ⎝⎛ ⎛⎜exp⎜ − D⎝ ⎝sub⋅LVT1eff2lΦ −V⎛ Nlx ⎞⎜ 1+−1⎟⎜ L ⎟⎝ eff ⎠VT1wtosWbseffΦ +seff2l− K' Ltw( K + K V )eff2ox⎞ ⎛ ⎟ + 2exp⎜ − D⎠ ⎝Vsubbseff3bLeff⎞ ⎛Dl⎟ + 2exp⎜ −2t ⎠ ⎝3LlVT1efftobseff⎞ ⎛ ⎟ + 2exp⎜ − D⎠ ⎝Leffl⎞⎞⎟⎟⎠⎠tToxΦW ' + WeffVT1w⎞⎞⎟⎟⎠⎠W( V −Φ)biefftweff( E tao+ E tabV bseff) V ds0ls' Ls⎞⎞⎟⎟⎠⎠( V −Φ)bi(2.1.25)swhere T ox dependence is introduced in the model parameters K 1 and K 2 toimprove the scalibility of V th model with respect to T ox . V th0ox , K 1ox and K 2oxare modeled asVth0ox= Vth0−K1⋅ΦsandKKKTox1 ox= 1⋅ToxmTox2 ox= K 2⋅ToxmT oxm is the gate oxide thickness at which parameters are extracted with adefault value of T ox .In Eq. (2.1.25), all V bs terms have been substituted with a V bseff expressionas shown in Eq. (2.1.26). This is done in order to set an upper bound for thebody bias value during simulations since unreasonable values can occur ifthis expression is not introduced (see Section 3.8 for details).2-14 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Mobility Model(2.1.26)Vbseff = Vbc + 05 .[ Vbs −Vbc − δ1+ ( Vbs −Vbc −δ1) 2 −4δ1Vbc]where δ 1 = 0.001V. The parameter V bc is the maximum allowable V bsvalue and is calculated from the condition of dV th /dV bs =0 for the V thexpression of 2.1.4, 2.1.5, and 2.1.6, and is equal to:Vbc2⎛ K1= 0.9⎜Φs−2⎝ 4K2⎞⎠2.2 Mobility ModelA good mobility model is critical to the accuracy of a MOSFET model. Thescattering mechanisms responsible for surface mobility basically include phonons,coulombic scattering, and surface roughness [11, 12]. For good quality interfaces,phonon scattering is generally the dominant scattering mechanism at roomtemperature. In general, mobility depends on many process parameters and biasconditions. For example, mobility depends on the gate oxide thickness, substratedoping concentration, threshold voltage, gate and substrate voltages, etc. Sabnisand Clemens [13] proposed an empirical unified formulation based on the conceptof an effective field E eff which lumps many process parameters and bias conditionstogether. E eff is defined byEeffQ=B+ ( Qn2)εsi(2.2.1)The physical meaning of E eff can be interpreted as the average electrical fieldexperienced by the carriers in the inversion layer [14]. The unified formulation ofmobility is then given byBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-15

Mobility Modelµeffµ=01 + ( E E )eff0ν(2.2.2)Values for µ 0 , E 0 , and ν were reported by Liang et al. [15] and Toh et al. [16] to bethe following for electrons and holesParameter Electron (surface) Hole (surface)µ 0 (cm 2 /Vsec) 670 160E 0 (MV/cm) 0.67 0.7ν 1.6 1.0Table 2-1. Typical mobility values for electrons and holes.For an NMOS transistor with n-type poly-silicon gate, Eq. (2.2.1) can be rewrittenin a more useful form that explicitly relates E eff to the device parameters [14]EeffVgs+ Vth≅6Tox(2.2.3)Eq. (2.2.2) fits experimental data very well [15], but it involves a very timeconsuming power function in SPICE simulation. Taylor expansion Eq. (2.2.2) isused, and the coefficients are left to be determined by experimental data or to beobtained by fitting the unified formulation. Thus, we have2-16 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Carrier Drift Velocity(mobMod=1) (2.2.4)µ oµ eff =V gsteff + 2Vthgsteff thUa UcVbseffU + 2+ +V 21 ( )( V) + b( )TOXTOXwhere V gst =V gs -V th . To account for depletion mode devices, another mobilitymodel option is given by the following(mobMod=2) (2.2.5)µ oµ eff =V gsteffgsteffUa UcVbseffU21 + ( + )( V) + b( )TOXTOXThe unified mobility expressions in subthreshold and strong inversion regions willbe discussed in Section 3.2.To consider the body bias dependence of Eq. 2.2.4 further, we have introduced thefollowing expression:(For mobMod=3) (2.2.6)µ oµ eff =V gsteff thgsteff thU + 2 VaU + 2 V 21 + [ ( V) + b( ) ]( 1 + UV c bseff)TOXTOX2.3 Carrier Drift VelocityCarrier drift velocity is also one of the most important parameters. The followingvelocity saturation equation [17] is used in the modelBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-17

Bulk Charge Effectµ eff Ev = , E < E1 + ( EE )sat= v ,E > Esatsatsat(2.3.1)The parameter E sat corresponds to the critical electrical field at which the carriervelocity becomes saturated. In order to have a continuous velocity model at E =E sat , E sat must satisfy:Esatv= 2 satµ eff(2.3.2)2.4 Bulk Charge EffectWhen the drain voltage is large and/or when the channel length is long, thedepletion "thickness" of the channel is non-uniform along the channel length. Thiswill cause V th to vary along the channel. This effect is called bulk charge effect[14].The parameter, A bulk , is used to take into account the bulk charge effect. Severalextracted parameters such as A 0 , B 0 , B 1 are introduced to account for the channellength and width dependences of the bulk charge effect. In addition, the parameterKeta is introduced to model the change in bulk charge effect under high substratebias conditions. It should be pointed out that narrow width effects have beenconsidered in the formulation of Eq. (2.4.1). The A bulk expression is given byAbulk⎛⎜= ⎜1+⎜ 2⎝K1oxΦ −Vsbseff⎛⎜⎜L⎝effA L0+ 2effXJXdep⎛⎜⎜1−AgsV⎝gsteff⎛⎜⎜⎝LeffL+ 2effXJXdep(2.4.1)2⎞ ⎞ ⎞⎞⎟ ⎟ B ⎟0⎟ 1+ ⎟⎟⋅⎟ ⎟Weff' + B1⎟ 1+KetaV⎠ ⎠ ⎠⎠bseff2-18 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Strong Inversion Drain Current (Linear Regime)where A 0 , A gs , B 0 , B 1 and Keta are determined by experimental data. Eq. (2.4.1)shows that A bulk is very close to unity if the channel length is small, and A bulkincreases as channel length increases.2.5 Strong Inversion Drain Current (LinearRegime)2.5.1 Intrinsic Case (R ds =0)In the strong inversion region, the general current equation at any point yalong the channel is given byI = WC ( V − A V ) vds ox gstbulk ( y) ( y)(2.5.1)The parameter V gst = (V gs - V th ), W is the device channel width, C ox is thegate capacitance per unit area, V(y) is the potential difference betweenminority-carrier quasi-Fermi potential and the equilibrium Fermi potentialin the bulk at point y, v(y) is the velocity of carriers at point y.With Eq. (2.3.1) (i.e. before carrier velocity saturates), the drain currentcan be expressed asµeffE ( y)Ids = WCox ( Vgs −Vth− AbulkV( y))1+E( y)Esat(2.5.2)Eq. (2.5.2) can be rewritten as followsBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-19

Strong Inversion Drain Current (Linear Regime)E( y)=µeffIdsWC ( V − AbulkV ( y)) − I Eoxgstdssat=dV ydy( )(2.5.3)By integrating Eq. (2.5.2) from y = 0 to y = L and V(y) = 0 to V(y) = V ds ,we arrive at the followingI C W 1L V E L V V A V Vds= µeff ox(gs−th− bulkds2)1+dssatds(2.5.4)The drain current model in Eq. (2.5.4) is valid before velocity saturates.For instances when the drain voltage is high (and thus the lateral electricalfield is high at the drain side), the carrier velocity near the drain saturates.The channel region can now be divided into two portions: one adjacent tothe source where the carrier velocity is field-dependent and the secondwhere the velocity saturates. At the boundary between these two portions,the channel voltage is the saturation voltage (V dsat ) and the lateralelectrical is equal to E sat . After the onset of saturation, we can substitute v= v sat and V ds = V dsat into Eq. (2.5.1) to get the saturation current:I = WC ( V − AbulkV ) vds ox gstdsatsat(2.5.5)By equating eqs. (2.5.4) and (2.5.5) at E = E sat and V ds = V dsat , we cansolve for saturation voltage V dsat(2.5.6)Vdsat=E L( V −V)sat gs thAbulkE L+ ( V −V)sat gs th2-20 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Strong Inversion Drain Current (Linear Regime)2.5.2 Extrinsic Case (R ds >0)Parasitic source/drain resistance is an important device parameter whichcan affect MOSFET performance significantly. As channel length scalesdown, the parasitic resistance will not be proportionally scaled. As a result,R ds will have a more significant impact on device characteristics. Modelingof parasitic resistance in a direct method yields a complicated drain currentexpression. In order to make simulations more efficient, the parasiticresistances is modeled such that the resulting drain current equation in thelinear region can be calculateed [3] asIds(2.5.9)V V= ds = dsRtotRch+ RdsW 1( Vgst − Abulk Vds 2 ) Vds= µ eff C oxL 1 + V E LW V A Vds ( sat )( gst − bulk ds 2 )1 + Rds µ eff CoxL 1 + Vds( EsatL)Due to the parasitic resistance, the saturation voltage V dsat will be largerthan that predicted by Eq. (2.5.6). Let Eq. (2.5.5) be equal to Eq. (2.5.9).V dsat with parasitic resistance R ds becomesb b acV dsat = − − − 42a2(2.5.10)The following are the expression for the variables a, b, and c:BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-21

Strong Inversion Current and Output Resistance (Saturation Regime)a = Abulk RdsCoxWvsat+ ( −1)Abulkλ2b =−( Vgst( − 1) + Abulk Esat L+3Abulk RdsCoxWvsatVgst)λ2c = Esat LVgst +2RdsCoxWvsatVgstλ = AV 1 gst + A22 1(2.5.11)The last expression for λ is introduced to account for non-saturation effectof the device. The parasitic resistance is modeled as:RdsR=dsw( 1+PrwgVgsteff+ Prwb( Φs−Vbseff− Φs)6 W( 10 W ') reff(2.5.11)The variable R dsw is the resistance per unit width, W r is a fitting parameter,P rwb and P rwg are the body bias and the gate bias coeffecients, repectively.2.6 Strong Inversion Current and OutputResistance (Saturation Regime)A typical I-V curve and its output resistance are shown in Figure 2-6. Consideringonly the drain current, the I-V curve can be divided into two parts: the linear regionin which the drain current increases quickly with the drain voltage and thesaturation region in which the drain current has a very weak dependence on thedrain voltage. The first order derivative reveals more detailed information aboutthe physical mechanisms which are involved during device operation. The outputresistance (which is the reciprocal of the first order derivative of the I-V curve)2-22 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Strong Inversion Current and Output Resistance (Saturation Regime)curve can be clearly divided into four regions with distinct R out vs. V dsdependences.The first region is the triode (or linear) region in which carrier velocity is notsaturated. The output resistance is very small because the drain current has a strongdependence on the drain voltage. The other three regions belong to the saturationregion. As will be discussed later, there are three physical mechanisms whichaffect the output resistance in the saturation region: channel length modulation(CLM) [4, 14], drain-induced barrier lowering (DIBL) [4, 6, 14], and the substratecurrent induced body effect (SCBE) [14, 18, 19]. All three mechanisms affect theoutput resistance in the saturation range, but each of them dominates in only asingle region. It will be shown next that channel length modulation (CLM)dominates in the second region, DIBL in the third region, and SCBE in the fourthregion.3.0142.5TriodeCLMDIBLSCBE12I ds(mA)2.01.51086R out(KOhms)1.040.520.00 1 2 3 4V ds(V)0Figure 2-6. General behavior of MOSFET output resistance.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-23

Strong Inversion Current and Output Resistance (Saturation Regime)Generally, drain current is a function of the gate voltage and the drain voltage. Butthe drain current depends on the drain voltage very weakly in the saturation region.A Taylor series can be used to expand the drain current in the saturation region [3].where(2.6.1)∂Ids ( Vgs, Vds)Ids ( Vgs, Vds ) = Ids ( Vgs, Vdsat) + ( Vds−Vdsat)∂VV VIds −≡dsatdsat ( 1 + )VAdsIdsat = Ids ( Vgs,Vdsat ) = WvsatCox ( Vgst − AbulkVdsat)(2.6.2)andVA∂ II ds −1= dsat ( )∂ Vds(2.6.3)The parameter V A is called the Early voltage and is introduced for the analysis ofthe output resistance in the saturation region. Only the first order term is kept in theTaylor series. We also assume that the contributions to the Early voltage from allthree mechanisms are independent and can be calculated separately.2-24 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Strong Inversion Current and Output Resistance (Saturation Regime)2.6.1 Channel Length Modulation (CLM)If channel length modulation is the only physical mechanism to be takeninto account, then according to Eq. (2.6.3), the Early voltage can becalculated byVACLM(2.6.4)∂ I LI ds ∂ −1 Abulk Esat L+Vgst∂ ∆L−1= dsat ( ) =( )∂ L ∂ VA E ∂ Vdsbulk sat dswhere ∆L is the length of the velocity saturation region; the effectivechannel length is L-∆L. Based on the quasi-two dimensionalapproximation, V ACLM can be derived as the followingVACLM=Abulk Esat L+VgstAbulkEsatl( Vds− Vdsat)(2.6.5)where V ACLM is the Early Voltage due to channel length modulationalone.The parameter P clm is introduced into the V ACLM expression not only tocompensate for the error caused by the Taylor expansion in the Earlyvoltage model, but also to compensate for the error in X J sinceand the junction depth X J can not generally be determined very accurately.Thus, the V ACLM becamel∝X JVACLM=1PclmAbulk Esat L+Vgst( Vds− Vdsat)AbulkEsatl(2.6.6)BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-25

Strong Inversion Current and Output Resistance (Saturation Regime)2.6.2 Drain-Induced Barrier Lowering (DIBL)As discussed above, threshold voltage can be approximated as a linearfunction of the drain voltage. According to Eq. (2.6.3), the Early voltagedue to the DIBL effect can be calculated as:(2.6.7)VADIBLCVADIBLC( Vgsteff+ 2vt)=θ t1+P V∂ Ids∂ Vth−= Idsat( ) = 1 ( V − (11 +∂ V ∂Vθ () A V Vrou ( DIBLCB bseff )thds th L gst⎛ AbulkVdsat⎞⎜1−⎟⎝ AbulkVdsat + Vgsteff + 2vt⎠bulkdsatDuring the derivation of Eq. (2.6.7), the parasitic resistance is assumed tobe equal to 0. As expected, V ADIBLC is a strong function of L as shown in Eq.(2.6.7). As channel length decreases, V ADIBLC decreases very quickly. Thecombination of the CLM and DIBL effects determines the output resistancein the third region, as was shown in Figure 2-6.Despite the formulation of these two effects, accurate modeling of theoutput resistance in the saturation region requires that the coefficientθ th (L) be replaced by θ rout (L). Both θ th (L) and θ rout (L) have the samechannel length dependencies but different coefficients. The expression forθ rout (L) is(2.6.8)( L) = P [exp( − D L / 2l ) + 2exp(− D L / l )] + Pθ rout diblc 1 rout t rout t diblc 2Parameters P diblc1 , P diblc2 , P diblcb and D rout are introduced to correct forDIBL effect in the strong inversion region. The reason why D vt0 is not2-26 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Strong Inversion Current and Output Resistance (Saturation Regime)equal to P diblc1 and D vt1 is not equal to D rout is because the gate voltagemodulates the DIBL effect. When the threshold voltage is determined, thegate voltage is equal to the threshold voltage. But in the saturation regionwhere the output resistance is modeled, the gate voltage is much larger thanthe threshold voltage. Drain induced barrier lowering may not be the sameat different gate bias. P diblc2 is usually very small (may be as small as8.0E-3). If P diblc2 is placed into the threshold voltage model, it will notcause any significant change. However it is an important parameter inV ADIBL for long channel devices, because P diblc2 will be dominant in Eq.(2.6.8) if the channel is long.2.6.3 Current Expression without Substrate Current InducedBody EffectIn order to have a continuous drain current and output resistanceexpression at the transition point between linear and saturation region, theV Asat parameter is introduced into the Early voltage expression. V Asat isthe Early Voltage at V ds = V dsat and is as follows:VAsat=(2.6.9)Esat L+ Vdsat + 2RdsvsatCoxW( Vgst − AbulkVds/ 2)1 + Abulk RdsvsatCoxWTotal Early voltage, V A , can be written as(2.6.10)VA1 1 −1= VAsat+ ( + )V VACLMADIBLBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-27

Strong Inversion Current and Output Resistance (Saturation Regime)The complete (with no impact ionization at high drain voltages) currentexpression in the saturation region is given byVds− VdsatIdso= WvsatCox ( Vgst − AbulkVdsat)( 1 + )VA(2.6.11)Furthermore, another parameter, P vag , is introduced in V A to account forthe gate bias dependence of V A more accurately. The final expression forEarly voltage becomesVAPvagV gsteff−= VAsat+ ( 1+ 1 1 1)( + )EsatLeff VACLM VADIBLC(2.6.12)2.6.4 Current Expression with Substrate Current Induced BodyEffectWhen the electrical field near the drain is very large (> 0.1MV/cm), someelectrons coming from the source will be energetic (hot) enough to causeimpact ionization. This creates electron-hole pairs when they collide withsilicon atoms. The substrate current I sub thus created during impactionization will increase exponentially with the drain voltage. A well knownI sub model [20] is given as:Isub=AiIBidsi( V ) ⎜⎟ ds−Vdsatexp −⎝ Vds−Vdsat⎠⎛B l⎞(2.6.13)2-28 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Strong Inversion Current and Output Resistance (Saturation Regime)The parameters A i and B i are determined from extraction. I sub will affectthe drain current in two ways. The total drain current will change because itis the sum of the channel current from the source as well as the substratecurrent. The total drain current can now be expressed [21] as followsI = Idso+ Ids⎡⎢= Idso⎢1+Bi⎢⎣ Aisub⎤( Vds− Vdsat)⎥Bl ⎥iexp( ) ⎥Vds− Vdsat⎦(2.6.14)The total drain current, including CLM, DIBL and SCBE, can be written as(2.6.15)Vds− VdsatVds− VdsatIds = WvsatCox ( Vgst − AbulkVdsat)( 1+)( 1+)V VASCBEwhere V ASCBE can also be called as the Early voltage due to the substratecurrent induced body effect. Its expression is the followingAVASCBE=BiBl iexp( )AiVds− Vdsat(2.6.16)From Eq. (2.6.16), we can see that V ASCBE is a strong function of V ds . Inaddition, we also observe that V ASCBE is small only when V ds is large. Thisis why SCBE is important for devices with high drain voltage bias. Thechannel length and gate oxide dependence of V ASCBE comes from V dsat andl. We replace Bi with PSCBE2 and Ai/Bi with PSCBE1/L to yield thefollowing expression for V ASCBEBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-29

Subthreshold Drain CurrentV1 PSCBE2 PSCBE1ASCBEl= exp( − )L V − Vdsdsat(2.6.17)The variables P scbe1 and P scbe2 are determined experimentally.2.7 Subthreshold Drain CurrentThe drain current equation in the subthreshold region can be expressed as [2, 3]IdsV V V Vdsgs−th−off= Is0 ( 1−exp( − )) exp( )vnv tttm(2.7.1)I= µs0 0WLqεsiNchv2φs2t(2.7.2)Here the parameter v t is the thermal voltage and is given by K B T/q. V off is theoffset voltage, as discussed in Jeng's dissertation [18]. V off is an importantparameter which determines the drain current at V gs = 0. In Eq. (2.7.1), theparameter n is the subthreshold swing parameter. Experimental data shows that thesubthreshold swing is a function of channel length and the interface state density.These two mechanisms are modeled by the following(2.7.3)C C V C V D L effDL eff( dsc + dscd ds + dscb bseff )⎛⎜exp( − VT + −⎞1 ) 2exp( VT1) ⎟Cd⎝ 2ltlt⎠ Cn= 1+ Nfactor++CoxCoxCitoxwhere the term2-30 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Effective Channel Length and WidthC C V C V D L effDL eff( dsc + dscd ds + dscb bseff )⎛⎜exp( − VT + −⎞1 ) 2 exp( VT1) ⎟⎝ 2ltlt⎠+represents the coupling capacitance between the drain or source to the channel.The parameters C dsc , C dscd and C dscb are extracted. The parameter C it in Eq. (2.7.3)is the capacitance due to interface states. From Eq. (2.7.3), it can be seen thatsubthreshold swing shares the same exponential dependence on channel length asthe DIBL effect. The parameter Nfactor is introduced to compensate for errors inthe depletion width capacitance calculation. Nfactor is determined experimentallyand is usually very close to 1.2.8 Effective Channel Length and WidthThe effective channel length and width used in all model expressions is givenbelowLeff= Ldrawn−2dLWeff= Wdrawn−2dWWeff= Wdrawn− 2dW(2.8.1)(2.8.2a)(2.8.2b)The only difference between Eq. (2.8.2a) and (2.8.2b) is that the former includesbias dependencies. The parameters dW and dL are modeled by the followingBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-31

Effective Channel Length and WidthdW = dW ' + dW VdW ' = WintgW+LlW lngsteffW+W+ dWwWwnb( Φ −V− Φ )sW+L WwlW ln WwnLlLwdL = L + + +L LwnL W Lbseffwlint ln LlnLwnLWs(2.8.3)(2.8.4)These complicated formulations require some explanation. From Eq. (2.8.3), thevariable W int models represents the tradition manner from which "delta W" isextracted (from the intercepts of straights lines on a 1/R ds vs. W drawn plot). Theparameters dW g and dW b have been added to account for the contribution of bothfront gate and back side (substrate) biasing effects. For dL, the parameter L intrepresents the traditional manner from which "delta L" is extracted (mainly fromthe intercepts of lines from a R ds vs. L drawn plot).The remaining terms in both dW and dL are included for the convenience of theuser. They are meant to allow the user to model each parameter as a function ofW drawn , L drawn and their associated product terms. In addition, the freedom tomodel these dependencies as other than just simple inverse functions of W and L isalso provided for the user. For dW, they are Wln and Wwn. For dL they are Lln andLwn.By default all of the above geometrical dependencies for both dW and dL areturned off. Again, these equations are provided for the convenience of the user. Assuch, it is up to the user to adopt the correct extraction strategy to ensure properuse.2-32 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Poly Gate Depletion Effect2.9 Poly Gate Depletion EffectWhen a gate voltage is applied to a heavily doped poly-silicon gate, e.g. NMOSwith n + poly-silicon gate, a thin depletion layer will be formed at the interfacebetween the poly-silicon and gate oxide. Although this depletion layer is very thindue to the high doping concentration of the poly-Si gate, its effect cannot beignored in the 0.1µm regime since the gate oxide thickness will also be very small,possibly 50Å or thinner.Figure 2-7 shows an NMOSFET with a depletion region in the n + poly-silicongate. The doping concentration in the n + poly-silicon gate is N gate and the dopingconcentration in the substrate is N sub . The gate oxide thickness is T ox . The depletionwidth in the poly gate is X p . The depletion width in the substrate is X d . If weassume the doping concentration in the gate is infinite, then no depletion regionwill exist in the gate, and there would be one sheet of positive charge whosethickness is zero at the interface between the poly-silicon gate and gate oxide.In reality, the doping concentration is, of course, finite. The positive charge nearthe interface of the poly-silicon gate and the gate oxide is distributed over a finitedepletion region with thickness X p . In the presence of the depletion region, thevoltage drop across the gate oxide and the substrate will be reduced, because partof the gate voltage will be dropped across the depletion region in the gate. Thatmeans the effective gate voltage will be reduced.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-33

Poly Gate Depletion EffectNgateFigure 2-7. Charge distribution in a MOSFET with the poly gate depletion effect.The device is in the strong inversion region.The effective gate voltage can be calculated in the following manner. Assume thedoping concentration in the poly gate is uniform. The voltage drop in the poly gate(V poly ) can be calculated as1qNN 2 gate poly Xpolypoly = XpolyEpoly=2 2εsi(2.9.1)where E poly is the maximum electrical field in the poly gate. The boundarycondition at the interface of poly gate and the gate oxide isε E = ε E = 2qεN gate Vox ox si poly si poly poly(2.9.2)2-34 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Poly Gate Depletion Effectwhere E ox is the electrical field in the gate oxide. The gate voltage satisfiesV −V−Φ = V + VgsFBspolyox(2.9.3)where V ox is the voltage drop across the gate oxide and satisfies V ox = E ox T ox .According to the equations (2.9.1) to (2.9.3), we obtain the following2( −V−Φ −V) −V= 0aVgsFBspolypoly(2.9.4)where (2.9.5)a =2εox22qεsiNgateToxBy solving the equation (2.9.4), we get the effective gate voltage (V gs_eff ) which isequal to:Vgs_eff( V −V−Φ )2 ⎛2qε⎞siNgateTox= +Φ +⎜ 2εox gs FB sV1+−1⎟FB s2 ⎜2ε⎟oxqεsiNgateTox⎝⎠(2.9.6)Figure 2-8 shows V gs_eff / V gs versus the gate voltage. The threshold voltage isassumed to be 0.4V. If T ox = 40 Å, the effective gate voltage can be reduced by 6%due to the poly gate depletion effect as the applied gate voltage is equal to 3.5V.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-35

Poly Gate Depletion Effect1.00Tox=80A80 ÅVgs_eff / VgsVgs_eff/Vgs0.95Tox=60A60 ÅTox=40AT = Å0.900.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0V gs(V)Vgs (V)Figure 2-8. The effective gate voltage versus applied gate voltage at different gateoxide thickness.The drain current reduction in the linear region as a function of the gate voltagecan now be determined. Assume the drain voltage is very small, e.g. 50mV. Thenthe linear drain current is proportional to C ox (V gs - V th ). The ratio of the linear draincurrent with and without poly gate depletion is equal to:I( Vgs_eff ) ( Vgs_eff − Vth)=I ( V ) ( V − V )dsdsgsgsth(2.9.7)Figure 2-9 shows I ds (V gs_eff ) / I ds (V gs ) versus the gate voltage using Eq. (2.9.7). Thedrain current can be reduced by several percent due to gate depletion.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-36

Poly Gate Depletion Effect1.00Tox=80AÅIds(Vgs_eff)/Ids(Vgs)Ids(Vgs_eff) / Ids(Vgs)0.95Tox=60AÅTox=40AT = Å0.900.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5Vgs V (V) (V)Figure 2-9. Ratio of linear region current with poly gate depletion effect and thatwithout.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-37

Poly Gate Depletion EffectBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-38

Poly Gate Depletion EffectBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-39

Poly Gate Depletion Effect2-40 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

CHAPTER 3: Unified I-V ModelThe development of separate model expressions for such device operation regimes assubthreshold and strong inversion were discussed in Chapter 2. Although theseexpressions can accurately describe device behavior within their own respective region ofoperation, problems are likely to occur between two well-described regions or withintransition regions. In order to circumvent this issue, a unified model should be synthesizedto not only preserve region-specific expressions but also to ensure the continuities ofcurrent and conductance and their derivatives in all transition regions as well. Such highstandards are kept in BSIM3v3.2.1 . As a result, convergence and simulation efficiencyare much improved.This chapter will describe the unified I-V model equations. While most of the parametersymbols in this chapter are explained in the following text, a complete description of all I-V model parameters can be found in Appendix A.3.1 Unified Channel Charge DensityExpressionSeparate expressions for channel charge density are shown below for subthreshold(Eq. (3.1.1a) and (3.1.1b)) and strong inversion (Eq. (3.1.2)). Both expressions arevalid for small V ds .BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 3-1

Unified Channel Charge Density ExpressionQ= Qchsubs0 0Vgs−Vthexp( )nvt(3.1.1a)where Q 0 isQ0= qεsiNchVoffv t exp(2− )φsnvtQchs0 = Cox( Vgs −Vth)(3.1.1b)(3.1.2)In both Eqs. (3.1.1a) and (3.1.2), the parameters Q chsubs0 and Q chs0 are the channelcharge densities at the source for very small Vds. To form a unified expression, aneffective (V gs -V th ) function named V gsteff is introduced to describe the channelcharge characteristics from subthreshold to strong inversionVgsteff⎡ Vgs−Vth⎤2 nvtln⎢1+exp( ) ⎥nvt=⎣ 2 ⎦2ΦsVgs −Vth − 2Voff1+ 2 n COXexp( −)qεsiNch2 nvt(3.1.3)The unified channel charge density at the source end for both subthreshold andinversion region can therefore be written asQC Vchs0 = ox gsteff(3.1.4)Figures 3-1 and 3-2 show the smoothness of Eq. (3.1.4) from subthreshold tostrong inversion regions. The V gsteff expression will be used again in subsequentsections of this chapter to model the drain current.3-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Unified Channel Charge Density ExpressionVgsteff (V)3.02.52.01.51.00.50.0-0.5Vgsteff Functionexp[(Vgs-Vth)/n*v t]Vgs=Vth-1.0(Vgs-Vth)-1.5-1.0 -0.5 0.0 0.5 1.0 1.5 2.0V gs -V th (V)Vgs-Vth (V)Figure 3-1. The V gsteff function vs. (V gs -V th ) in linear scale.42Log(Vgsteff)0Log(Vgsteff)-2-4-6-8-10-12-14(Vgs-Vth)exp[(Vgs-Vth)/n*v t]Vgs=Vth-16-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5Vgs-Vth (V)Vgs-Vth (V)Figure 3-2. V gsteff function vs. (V gs -V th ) in log scale.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 3-3

Unified Channel Charge Density ExpressionEq. (3.1.4) serves as the cornerstone of the unified channel charge expression atthe source for small V ds . To account for the influence of V ds , the V gsteff functionmust keep track of the change in channel potential from the source to the drain. Inother words, Eq. (3.1.4) will have to include a y dependence. To initiate thisformulation, consider first the re-formulation of channel charge density for thecase of strong inversionQchs( y) = Cox( Vgs −Vth −AbulkVF ( y))(3.1.5)The parameter V F (y) stands for the quasi-Fermi potential at any given point y,along the channel with respect to the source. This equation can also be written asQ = Q 0 + ∆Qchs( y) chs chs( y)(3.1.6)The term ∆Q chs (y) is the incremental channel charge density induced by the drainvoltage at point y. It can be expressed as∆Q =−CoxA Vchs( y) bulk F ( y)(3.1.7)For the subthreshold region (V gs

Unified Channel Charge Density ExpressionA Taylor series expansion of the right-hand side of Eq. (3.1.8) yields the following(keeping only the first two terms)Qchsubs( y)AbulkVF ( y)= Qchsubs0( 1−)nvt(3.1.9)Analogous to Eq. (3.1.6), Eq. (3.1.9) can also be written asQ = Q 0+∆Qchsubs( y) chsubs chsubs( y)(3.1.10)The parameter ∆Q chsubs (y) is the incremental channel charge density induced bythe drain voltage in the subthreshold region. It can be written as∆Qchsubs( y)AbulkVF ( y)=− Qchsubs0nvt(3.1.11)Note that Eq. (3.1.9) is valid only when V F (y) is very small, which is maintainedfortunately, due to the fact that Eq. (3.1.9) is only used in the linear regime (i.e. V ds≤2v t ).Eqs. (3.1.6) and (3.1.10) both have drain voltage dependencies. However, they aredecupled and a unified expression for Q ch (y) is needed. To obtain a unifiedexpression along the channel, we first assume∆Qch( y)=∆Q∆Q∆Q+ ∆Qchs( y) chsubs( y)chs( y) chsubs( y)(3.1.12)Here, ∆Q ch (y) is the incremental channel charge density induced by the drainvoltage. Substituting Eq. (3.1.7) and (3.1.11) into Eq. (3.1.12), we obtainBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 3-5

Unified Mobility Expression∆QVF( y)Vb Qch ( y ) = chs0(3.1.13)where V b = (V gsteff + n*v t )/A bulk . In order to remove any association between thevariable n and bias dependencies (V gsteff ) as well as to ensure more precisemodeling of Eq. (3.1.8) for linear regimes (under subthreshold conditions), n isreplaced by 2. The expression for V b now becomesVb=V+ 2vtAbulkgsteff(3.1.14)A unified expression for Q ch (y) from subthreshold to strong inversion regimes isnow at handQch( y)VF( y)= Qchs0( 1−)Vb(3.1.15)The variable Q chs0 is given by Eq. (3.1.4).3.2 Unified Mobility ExpressionUnified mobility model based on the V gsteff expression of Eq. 3.1.3 is described inthe following.3-6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Unified Linear Current Expression(mobMod = 1) (3.2.1)µ oµ eff =Vgsteff+ 2Vthgsteff thUa UcVbseffU V + 2 V 21 + ( + )( ) + b( )TOXTOXTo account for depletion mode devices, another mobility model option is given bythe following(mobMod = 2) (3.2.2)µ oµ eff =VgsteffgsteffUa UcVbseffUV 21 + ( + )( ) + b( )TOXTOXTo consider the body bias dependence of Eq. 3.2.1 further, we have introduced thefollowing expression(For mobMod = 3) (3.2.3)µeffµ o=gsteff thgsteff thU V + 2 VaU V + 2 V 21 + [ ( ) + b( ) ]( 1 + UV c bseff)TOXTOX3.3 Unified Linear Current Expression3.3.1 Intrinsic case (Rds=0)Generally, the following expression [2] is used to account for both drift anddiffusion currentBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 3-7

Unified Linear Current ExpressionI= WQ µd( y) ch( y) ne( y)dVdyF( y)(3.3.1)where the parameter u ne (y) can be written asµ effµ ne( y)=E1 +Eysat(3.3.2)Substituting Eq. (3.3.2) in Eq. (3.3.1) we getId( y)VF y µ eff= WQchso( 1 − )VbE1 +EysatdVdy( ) F( y)(3.3.3)Eq. (3.3.3) resembles the equation used to model drain current in the stronginversion regime. However, it can now be used to describe the currentcharacteristics in the subthreshold regime when V ds is very small (V ds

Unified Vdsat Expression3.3.2 Extrinsic Case (R ds > 0)The current expression when R ds > 0 can be obtained based on Eq. (2.5.9)and Eq. (3.3.4). The expression for linear drain current from subthresholdto strong inversion is:IdsIdso=R I1 +Vds dsods(3.3.5)3.4 Unified Vdsat Expression3.4.1 Intrinsic case (R ds =0)To get an expression for the electric field as a function of y along thechannel, we integrate Eq. (3.3.1) from 0 to an arbitrary point y. The result isas followsEy=IIdso( WQchs0µeff − )Esatdso2Ids WQchs µ eff y−Vb2 0 0(3.4.1)If we assume that drift velocity saturates when Ey=Esat, we get thefollowing expression for I dsat(3.4.2)Idsat=µ eff chs0sat bW Q E LV2 LE ( satL+Vb)BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 3-9

Unified Vdsat ExpressionLet V ds =V dsat in Eq. (3.3.4) and set this equal to Eq. (3.4.2), we get thefollowing expression for V dsat(3.4.3)Vdsat=EsatL( Vgsteff + 2vt)AbulkEsatL+ Vgsteff + 2vt3.4.2 Extrinsic Case (R ds >0)The V dsat expression for the extrinsic case is formulated from Eq. (3.4.3)and Eq. (2.5.10) to be the followingb b acVdsat = − − 2− 42a(3.4.4a)wherea = A W ν C R + ( −1)Aλ1bulk 2 eff sat ox DS bulk(3.4.4b)(3.4.4c)⎛2b=− ⎜( V + 2v)( − 1 ) + A E L + 3 A ( V + 2 v)W ν C R⎝λgsteff t bulk sat eff bulk gsteff t eff sat ox DS⎞⎟⎠2c = ( V + 2v ) E L + 2( V + 2v)W ν C Rgsteff t sat eff gsteff t eff sat ox DSλ = AVgsteff+ A1 2(3.4.4d)(3.4.4e)3-10 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Unified Saturation Current ExpressionThe parameter λ is introduced to account for non-saturation effects.Parameters A 1 and A 2 can be extracted.3.5 Unified Saturation Current ExpressionA unified expression for the saturation current from the subthreshold to the stronginversion regime can be formulated by introducing the V gsteff function into Eq.(2.6.15). The resulting equations are the followingIdsI=R I1 +Vdso( Vdsat)ds dso( Vdsat)dsat⎛ Vds− VdsatVdsV⎜ +⎞ −1 ⎟⎛⎜1+⎝ VA⎠⎝VASCBEdsat⎞⎟⎠(3.5.1)whereVAPvagVgsteff1 1 −1= VAsat+ ( 1+ )( + )EsatLeff VACLM VADIBLC(3.5.2)VAsat=(3.5.3)AbulkVdsatEsatLeff + Vdsat + 2RDSνsatCoxWeff Vgsteff[1−2 ( Vgsteff+ 2 vt) ]2/λ− 1+RDSνsatCoxWeffAbulkVACLM=A E L + VPCLMAbulkEsatlitlbulk sat eff gsteff( Vds− Vdsat)(3.5.4)BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 3-11

Single Current Expression for All Operating Regimes of Vgs and VdsVADIBLC=θ( Vgsteff+ 2vt)t 1 + P Vrou ( DIBLCB bseff )⎛⎜1−⎝AbulkVdsat⎞⎟AbulkVdsat + Vgsteff + 2vt⎠(3.5.5)⎡LL ⎤exp( ) exp( ) P⎣2ll ⎦⎥ +effeffθrout = PDIBLC 1 DROUTDROUT⎢− + 2 −t 0 t 0DIBLC2(3.5.6)V−Plitlexp⎛ ⎞⎜ ⎟⎝ Vds− Vdsat⎠1 scbe2 scbe1ASCBEP=Leff(3.5.7)3.6 Single Current Expression for AllOperating Regimes of V gs and V dsThe V gsteff function introduced in Chapter 2 gave a unified expression for the lineardrain current from subthreshold to strong inversion as well as for the saturationdrain current from subthreshold to strong inversion, separately. In order to link thecontinuous linear current with that of the continuous saturation current, a smoothfunction for V ds is introduced. In the past, several smoothing functions have beenproposed for MOSFET modeling [22-24]. The smoothing function used in BSIM3is similar to that proposed in [24]. The final current equation for both linear andsaturation current now becomesIdsI=R I1 +Vdso( Vdseff )ds dso( Vdseff )dseff⎛ Vds− VdseffVdsV⎜ +⎞ −1 ⎟⎛⎜1+⎝ VA⎠⎝VASCBEdseff⎞⎟⎠(3.6.1)Most of the previous equations which contain V ds and V dsat dependencies are nowsubstituted with the V dseff function. For example, Eq. (3.5.4) now becomes3-12 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Single Current Expression for All Operating Regimes of Vgs and Vds(3.6.2)VACLM=A E L + VPCLMAbulkEsatlitlbulk sat eff gsteff( Vds−Vdseff)Similarly, Eq. (3.5.7) now becomesV⎛ −Plitl⎞exp⎜⎟⎝ Vds−Vdseff⎠1 scbe2 scbe1ASCBEP=Leff(3.6.3)The V dseff expression is written as2( δ ( δ)4δ)1V = V − V −V − + V −V − + V2dseff dsat dsat ds dsat ds dsat(3.6.4)The expression for V dsat is that given under Section 3.4. The parameter δ in theunit of volts can be extracted. The dependence of V dseff on V ds is given in Figure 3-3. The V dseff function follows V ds in the linear region and tends to V dsat in thesaturation region. Figure 3-4 shows the effect of δ on the transition region betweenlinear and saturation regimes.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 3-13

KAPITEL 7RESULTAT OCH REKOMMENDATIONERKapitlet inleds med en återgivning av problemformuleringen, studiens övergripande forskningsfråga,syfte och frågeställningar. Vidare presteras studiens resultat till var och en av de tre frågeställningarna.Därefter ges rekommendationer samt förslag till vidare studier. Avslutningsvis sammanfattas kapitlet.7. Inledning till studiens resultatSynen på mat har förändrats under de senaste decennierna och maten värdesätts idaginte i lika stor utsträckning som förr, vilket anses vara en bidragande orsak till attmatsvinn uppkommer. Idag slänger Sveriges befolkning årligen 2,3 miljoner ton mat.Även skolmatsalars matsvinn är högt då det årligen slängs 3,2 miljoner kilo mat tillföljd av att elever inte äter upp den mat de tagit till sig på tallriken. Med detta problem iåtanke presenteras studiens övergripande forskningsfråga, syfte och frågeställningar föratt underlätta förståelsen för studiens resultat.Studiens övergripande forskningsfrågaKan matproduktion och dess påverkan på natur och samhälle uppnå en hållbarutveckling med tanke på den respektlösa inställning människor har gentemot att slängamat i onödan?Studiens syfteAtt undersöka vilka incitament som kan bidra till en attityd- och beteendeförändring hoselever med avsikt att reducera matsvinn.Frågeställning 1Vad har elever för attityd gentemot att slänga mat?59

A Note on Vbs3-16 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

CHAPTER 4: Capacitance ModelingAccurate modeling of MOSFET capacitance plays equally important role as that of theDC model. This chapter describes the methodology and device physics considered in bothintrinsic and extrinsic capacitance modeling in BSIM3v3.2.2. Detailed model equationsare given in Appendix B. One of the important features of BSIM3v3.2 is introduction of anew intrinsic capacitance model (capMod=3 as the default model), considering the finitecharge thickness determined by quantum effect, which becomes more important forthinner T ox CMOS technologies. This model is smooth, continuous and accuratethroughout all operating regions.4.1 General Description of CapacitanceModelingBSIM3v3.2.2 models capacitance with the following general features:• Separate effective channel length and width are used for capacitance models.• The intrinsic capacitance models, capMod=0 and 1, use piece-wise equations.capMod=2 and 3 are smooth and single equation models; therefore both charge andcapacitance are continous and smooth over all regions.• Threshold voltage is consistent with DC part except for capMod=0, where a longchannelV th is used. Therefore, those effects such as body bias, short/narrow channeland DIBL effects are explicitly considered in capMod=1, 2, and 3.• Overlap capacitance comprises two parts: (1) a bias-independent component whichmodels the effective overlap capacitance between the gate and the heavily dopedsource/drain; (2) a gate-bias dependent component between the gate and the lightlydoped source/drain region.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-1

Geometry Definition for C-V Modeling• Bias-independent fringing capacitances are added between the gate and source as wellas the gate and drain.Name Function Default UnitcapMod Flag for capacitance models 3 (True)vfbcv the flat-band voltage for capMod = 0 -1.0 (V)acdeExponential coefficient for X DC for accumulation and depletionregions1 (m/V)moin Coefficient for the surface potential 15 (V 0.5 )cgso Non-LDD region G/S overlap C per channel length Calculated F/mcgdo Non-LDD region G/D overlap C per channel length Calculated F/mCGS1 Lightly-doped source to gate overlap capacitance 0 (F/m)CGD1 Lightly-doped drain to gate overlap capacitance 0 (F/m)CKAPPA Coefficient for lightly-doped overlap capacitance 0.6CF Fringing field capacitance equation(4.5.1)(F/m)CLC Constant term for short channel model 0.1 µmCLE Exponential term for short channel model 0.6DWC Long channel gate capacitance width offset Wint µmDLC Long channel gate capacitance length offset Lint µmTable 4-1. Model parameters in capacitance models.4.2 Geometry Definition for C-V ModelingFor capacitance modeling, MOSFET’s can be divided into two regions: intrinsicand extrinsic. The intrinsic capacitance is associated with the region between themetallurgical source and drain junction, which is defined by the effective length4-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Geometry Definition for C-V Modeling(L active ) and width (W active ) when the gate to S/D region is at flat band voltage.L active and W active are defined by Eqs. (4.2.1) through (4.2.4).Lactive= Ldrawn−2δLeff(4.2.1)Wactive= Wdrawn−2δWeff(4.2.2)δLeffLlc= DLC+LLwcW+ +Lln LwnLwlclnL WLwn(4.2.3)δWeffWlc= DWC+LWwcW+ +W ln WwnWwlcW lnL WWwn(4.2.4)The meanings of DWC and DLC are different from those of Wint and Lint in the I-V model. L active and W active are the effective length and width of the intrinsicdevice for capacitance calculations. Unlike the case with I-V, we assumed thatthese dimensions have no voltage bias dependence. The parameter δL eff is equal tothe source/drain to gate overlap length plus the difference between drawn andactual POLY CD due to processing (gate printing, etching and oxidation) on oneside. Overall, a distinction should be made between the effective channel lengthextracted from the capacitance measurement and from the I-V measurement.Traditionally, the L eff extracted during I-V model characterization is used to gaugea technology. However this L eff does not necessarily carry a physical meaning. It isjust a parameter used in the I-V formulation. This L eff is therefore very sensitive tothe I-V equations used and also to the conduction characteristics of the LDDBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-3

Methodology for Intrinsic Capacitance Modelingregion relative to the channel region. A device with a large L eff and a smallparasitic resistance can have a similar current drive as another with a smaller L effbut larger R ds . In some cases L eff can be larger than the polysilicon gate lengthgiving L eff a dubious physical meaning.The L active parameter extracted from the capacitance method is a closerrepresentation of the metallurgical junction length (physical length). Due to thegraded source/ drain junction profile the source to drain length can have a verystrong bias dependence. We therefore define L active to be that measured at gate tosource/drain flat band voltage. If DWC, DLC and the newly-introduced length/width dependence parameters (Llc, Lwc, Lwlc, Wlc, Wwc and Wwlc) are notspecified in technology files, BSIM3v3.2.2 assumes that the DC bias-independentL eff and W eff (Eqs. (2.8.1) - (2.8.4)) will be used for C-V modeling, and DWC,DLC,Llc, Lwc, Lwlc, Wlc, Wwc and Wwlc will be set equal to the values of theirDC counterparts (default values).4.3 Methodology for Intrinsic CapacitanceModeling4.3.1 Basic FormulationTo ensure charge conservation, terminal charges instead of the terminalvoltages are used as state variables. The terminal charges Q g , Q b , Q s , andQ d are the charges associated with the gate, bulk, source, and draintermianls, respectively. The gate charge is comprised of mirror chargesfrom these components: the channel inversion charge (Q inv ), accumulationcharge (Q acc ) and the substrate depletion charge (Q sub ).4-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Methodology for Intrinsic Capacitance ModelingThe accumulation charge and the substrate charge are associated with thesubstrate while the channel charge comes from the source and drainterminals( )⎧Q =− Q + Q + Q⎪⎨Qb = Qacc + Qsub⎪⎩Qinv = Qs + Qdg sub inv acc(4.3.1)The substrate charge can be divided into two components - the substratecharge at zero source-drain bias (Q sub0 ), which is a function of gate tosubstrate bias, and the additional non-uniform substrate charge in thepresence of a drain bias (δQ sub ). Q g now becomes( )Q =− Q + Q + Q + Qg inv acc sub0 δsub(4.3.2)The total charge is computed by integrating the charge along the channel.The threshold voltage along the channel is modified due to the nonuniformsubstrate charge byth( y) = V th( 0) + ( A bulk − ) V yV 1(4.3.3)⎧⎪Qc= W⎪⎪⎨Qg= W⎪⎪⎪Qb= W⎪⎩Lactive∫Lactive∫Lactive∫q dy = −Wactive cactive ox0 0q dy = Wactive g active ox0 0q dy = −WCCCactive bactive ox0 0LLactive∫( Vgt− AbulkVy)active∫( Vgt+ Vth−VFB− Φs−Vy)Ldydyactive∫( Vth−VFB− Φs+ ( Abulk−1)Vy)dy(4.3.4)BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-5

Methodology for Intrinsic Capacitance ModelingSubstituting the followingdydV yy= ε( ) yand(4.3.5)WactiveµeffCox⎛ Abulk⎞Ids= ⎜Vgt− V ds ⎟Vds= W activeµ effC oxV gt− A bulkV yEL ⎝ 2 ⎠activeinto Eq. (4.3.4), we have the following upon integration⎧⎪⎪Q⎪⎪⎪⎪⎪⎨Q⎪⎪⎪⎪Q⎪⎪⎪⎪⎩cgb= −W= −Q= −Qactivesub 0gL− Qactive+ Wc=CactiveQoxsub⎛⎜⎜V⎜⎜⎝Lgtactive−C+ Qoxsub 0A2bulkVds⎛⎜⎜ VVgt−⎜ 2⎜⎝+ QaccAbulkV+⎛ A12 ⎜Vgt−⎝ 2ds2dsbulkV2dsAbulkV+⎛ A12 ⎜Vgt−⎝ 22bulkds(4.3.6)⎞⎟⎟⎞ ⎟⎟ ⎟⎠ ⎠Vds⎞⎟⎟⎞ ⎟⎟ ⎟⎠ ⎠where4-6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Methodology for Intrinsic Capacitance Modeling(4.3.7)⎧Q⎪⎪⎨⎪δQ⎪⎪⎩sub 0sub= −W= WactiveactiveLLactiveactiveCox2εqNsi⎛⎜⎜ 1 − A⎜ 2⎜⎝subbulk( 2Φ− V )VdsBbsAbulk+⎛12⎜V⎝( A − 1)gtbulk−A2bulkVVdsds⎞2 ⎟⎟⎞ ⎟⎟ ⎟⎠ ⎠The inversion charges are supplied from the source and drain electrodessuch that Q inv = Q s + Q d . The ratio of Q d and Q s is the charge partitioningratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60(XPART = 0, 0.5 and 1) which are the ratios of Q d to Q s in the saturationregion. We will revisit charge partitioning in Section 4.3.4.All capacitances are derived from the charges to ensure chargeconservation. Since there are four terminals, there are altogether 16components. For each componentCijQi= ∂ ∂Vj(4.3.8)where i and j denote the transistor terminals. In addition∑iCij∑= C = 0j4.3.2 Short Channel ModelIn deriving the long channel charge model, mobility is assumed to beconstant with no velocity saturation. Therefore in saturation region(V ds ≥V dsat ), the carrier density at the drain end is zero. Since no channellength modulation is assumed, the channel charge will remain a constantthroughout the saturation region. In essence, the channel charge in theijBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-7

Methodology for Intrinsic Capacitance Modelingsaturation region is assumed to be zero. This is a good approximation forlong channel devices but fails when L eff < 2 µm. If we define a drain bias,V dsat,cv , in which the channel charge becomes a constant, we will find thatV dsat,cv in general is larger than V dsat but smaller than the long channel V dsat ,given by V gt /A bulk . However, in old long channel charge models, V dsat,cv isset to V gt /A bulk independent of channel length. Consequently, C ij /L eff has nochannel length dependence (Eqs. (4.3.6), (4.37)). A pseudo short channelmodification from the long channel has been used in the past. It involvedthe parameter A bulk in the capacitance model which was redefined to beequal to V gt /V dsat , thereby equating V dsat,cv and V dsat . This overestimated theeffect of velocity saturation and resulted in a smaller channel capacitance.The difficulty in developing a short channel model lies in calculating thecharge in the saturation region. Although current continuity stipulates thatthe charge density in the saturation region is almost constant, it is difficultto calculate accurately the length of the saturation region. Moreover, due tothe exponentially increasing lateral electric field, most of the charge in thesaturation region are not controlled by the gate electrode. However, onewould expect that the total charge in the channel will exponentiallydecrease with drain bias. Experimentally,VV,< V,< V,=active →∞Agsteff ,cvdsat iv dsat cv dsat iv Lbulk(4.3.9)and V dsat,cv is modeled by the following4-8 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Methodology for Intrinsic Capacitance ModelingVcdsat , =dsat,cvAbulkVgsteff ,cv⎛ CLC+ ⎛ ⎝ ⎜ ⎞1⎜⎟⎝ Lactive⎠CLE⎞⎟⎠(4.3.10a)(4.3.10b)Vgsteff,cv⎛ ⎛V= noff⋅nv⎜+⎜tln 1 exp⎝ ⎝gs−Vth−voffcv⎞⎞⎟⎟noff⋅nvt ⎠⎠Parameters noff and voffcv are introduced to better fit measured data abovesubthreshold regions. The parameter A bulk is substituted A bulk0 in the longchannel equation byAbulk⎛' = Abulk+ ⎛ ⎝ ⎜ ⎞⎜⎟⎝ Lactive⎠⎞⎟⎠(4.3.11)0 1 CLC CLE bseff(4.3.11a)Abulk⎛=⎜1+⎜ 2⎝Ks1oxΦ −Vbseff⎛⎜⎜⎝LeffA L0+ 2effXJXdepB ⎞⎞0 ⎟⎟1+ ⋅Weff' + B ⎟⎟11+KetaV⎠⎠In (4.3.11), parameters CLC and CLE are introduced to consider channellengthmodulation.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-9

Methodology for Intrinsic Capacitance Modeling4.3.3 Single Equation FormulationTraditional MOSFET SPICE capacitance models use piece-wise equations.This can result in discontinuities and non-smoothness at transition regions.The following describes single-equation formulation for charge,capacitance and voltage modeling in capMod=2 and 3.(a) Transition from depletion to inversion regionThe biggest discontinuity is the inversion capacitance at threshold voltage.Conventional models use step functions and the inversion capacitancechanges abruptly from 0 to C ox . Concurrently, since the substrate charge isa constant, the substrate capacitance drops abruptly to 0 at thresholdvoltage. Both of these effects can cause oscillation during circuitsimulation. Experimentally, capacitance starts to increase almostquadratically at ~0.2V below threshold voltage and levels off at ~0.3Vabove threshold voltage. For analog and low power circuits, an accuratecapacitance model around the threshold voltage is very important.The non-abrupt channel inversion capacitance and substrate capacitancemodel is developed from the I-V model which uses a single equation toformulate the subthreshold, transition and inversion regions. The newchannel inversion charge model can be modified to any charge model bysubstituting V gt with V gsteff,cv as in the following( ) = Q( )QVgtV gsteff , CV(4.3.12)Capacitance now becomes4-10 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Methodology for Intrinsic Capacitance Modeling( ) = C( V )C Vgtgsteff,CV∂VVgsteff,CVgs,ds,bs(4.3.13)The “inversion” charge is always non-zero, even in the accumulationregion. However, it decreases exponentially with gate bias in thesubthreshold region.(b) Transition from accumulation to depletion regionAn effective flatband voltage V FBeff is used to smooth out the transitionbetween accumulation and depletion regions. It affects the accumulationand depletion charges(4.3.14)2{ V3 + V3+ 4δ3vfb} whereV3= vfb −Vgs+ Vbseff−δ3;= 0. VVFBeff = vfb − 0.5δ302vfb= Vth−Φs−K1oxΦ −Vsbseff(4.3.15)In BSIM3v3.2.2, a bias-independent V th is used to calculate vfb for capMod = 1, 2and 3. For capMod = 0, Vfbcv is used instead (refer to the appendices).Qsub0( )Q =−W L C V −vfbacc active active ox FBeff( V −V−V−V)2K ⎛⎜41oxgs FBeff= −WactiveLactiveCox⋅ −1+1+⎜22 K⎝1oxgsteffCV ,(4.3.16)(4.3.17)bseff⎞⎟⎟⎠BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-11

Methodology for Intrinsic Capacitance Modeling(c) Transition from linear to saturation regionAn effective V ds , V cveff , is used to smooth out the transition between linearand saturation regions. It affects the inversion charge.(4.3.18)2{ V4+ V4+ 4δ4Vdsat,cv} whereV4= Vdsat, cv−Vds−δ4;0. VVcveff = Vdsat, cv−0.5δ4= 02⎛⎜2 2A A Vbulkbulk cveffQinv =−Wactive LactiveC ⎜⎛' ⎞ 'ox ⎜Vgsteff− Vcveff ⎟ +,cv⎜⎝2 ⎠ ⎛ Abulk'⎜12⎜Vgsteff−,cv V⎝⎝ 2(4.3.19)cveff⎞⎟⎟⎞⎟⎟⎠⎟⎠δQ = W L Csub active active ox⎛⎜⎜1−A⎜ 2⎜⎝bulk( 1−)2bulk bulk cveff' A ' A ' VVcveff−⎛ Abulk'12⎜Vgsteff,cv− V⎝ 2(4.3.20)Below is a list of all the three partitioning schemes for the inversioncharge:(i) The 50/50 charge partitionThis is the simplest of all partitioning schemes in which the inversioncharges are assumed to be contributed equally from the source and drainnodes.cveff⎞⎟⎟⎞⎟⎟⎠⎟⎠4-12 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Methodology for Intrinsic Capacitance Modeling⎛⎜W L C AAactive active oxQs Qd QinvVbulk= = =− ⎜ '05 .gsteff− Vcveff+⎜,cv2 2 ⎛⎜12⎜V⎝⎝(4.3.21)2 2bulk'Vcveffgsteff ,cvAbulk'− V2(ii) The 40/60 channel-charge partitionThis is the most physical model of the three partitioning schemes in whichthe channel charges are allocated to the source and drain terminals byassuming a linear dependence on the position y.cveff⎞⎟⎟⎞⎟⎟⎠⎟⎠Lactive⎧⎛Qs = Wactive qc⎜−⎪∫ 10⎝⎨Lactive⎪yQd = Wactive qc⎩⎪ ∫L0activeyLactivedy⎞⎟ dy⎠(4.3.22)WQs= −⎛2⎜V⎝activegsteffCVLactiveCoxAbulk'− V2cveff(4.3.23)2 23⎞( A ' V ) − ( A V ) ⎟⎠⎛ 3 4 2 2⎜V−+2 gsteffCVVgsteffCVAbulk'VcveffVgsteffCVbulk cveffbulk'⎞ ⎝ 3315⎟⎠(4.3.24)Wactive Lactive CoxQd=−⎛ 3 5Vgsteffcv Vgsteff ( A V ) V ( A V ) ( A V )A cv 22 13⎜ −bulk' cveff+gsteff cv bulk' cveff−bulk'⎞2cveff ⎟⎛bulk'⎞ ⎝ 35 ⎠2⎜Vgsteffcv− Vcveff ⎟⎝ 2 ⎠cveff(iii) The 0/100 Charge PartitionIn fast transient simulations, the use of a quasi-static model may result in alarge unrealistic drain current spike. This partitioning scheme is developedto artificially suppress the drain current spike by assigning all inversionBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-13

Charge-Thickness Capacitance Modelcharges in the saturation region to the source electrode. Notice that thischarge partitioning scheme will still give drain current spikes in the linearregion and aggravate the source current spike problem.⎛( )Q W L C V A V A V2⎜gstefcvf bulk cveff bulk cveffs=− ⎜gsteff,c ''active active ox+ −2 4 ⎛ Abulk'⎜24⎜Vgsteff,cgsteffcv− V⎝⎝ 2cveff(4.3.25)⎞⎟⎟⎞⎟⎠⎟⎠⎛⎜Q W L C V A V A Vd=− ⎜gsteff,c3 'active active ox− +2 4 ⎛ A⎜8⎜Vgsteffcv−⎝⎝gsteff,c2( ' )gsteffcv bulk cveff bulk cveffbulk2'V(4.3.26)cveff⎞⎟⎟⎞⎟⎠⎟⎠(d) Bias-dependent threshold voltage effects on capacitanceConsistent Vth between DC and CV is important for acurate circuitsimulation. capMod=1, 2 and 3 use the same Vth as in the DC model.Therefore, those effects, such as body bias, DIBL and short-channel effectsare all explicitly considered in capacitance modeling. In deriving thecapacitances additional differentiations are needed to account for thedependence of threshold voltage on drain and substrate biases.4.4 Charge-Thickness Capacitance ModelCurrent MOSFET models in SPICE generally overestimate the intrinsiccapacitance and usually are not smooth at V fb and V th . The discrepancy is more4-14 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Charge-Thickness Capacitance Modelpronounced in thinner T ox devices due to the assumption of inversion andaccumulation charge being located at the interface. The charge sheet model or theband-gap(E g )-reduction model of quantum effect [31] improves theand thusthe V th modeling but is inadequate for CV because they assume zero chargethickness. Numerical quantum simulation results in Figure 4-1 indicate thesignificant charge thickness in all regions of the CV curves [32].This section describes the concepts used in the charge-thichness model (CTM).Appendix B lists all charge equations. A full report and anaylsis of the CTM modelcan be found in [32].Φ BNormalized Charge Distribution0.150.100.050.00EDCgg (µF/cm 2 )1.0E0.8 A0.60.4B DC0.2C -4 -3 -2 -1 0 1 2 3Vgs (V)ATox=30ANsub=5e17cm -3B0 20 40 60Depth (A)Figure 4-1. Charge distribution from numerical quantum simulations show significantcharge thickness at various bias conditions shown in the inset.CTM is a charge-based model and therefore starts with the DC charge thicknss,X DC . The charge thicknss introduces a capacitance in series with C ox as illustratedin Figure 4-2, resulting in an effective C ox , C oxeff . Based on numerical selfconsistentsolution of Shrodinger, Poisson and Fermi-Dirac equations, universaland analytical X DC models have been developed. C oxeff can be expressed asBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-15

Charge-Thickness Capacitance Model(4.4.1)CoxeffC=CoxoxCcen+ Ccenwhereε=CsicenXDCVgsVgseΦsCoxPoly depl.Cacc Cdep CinvBFigure 4-2. Charge-thickness capacitance concept in CTM. V gse accounts for the polydepletion effect.(i) X DC for accumulation and depletionThe DC charge thickness in the accumulation and depletion regions can beexpressed by [32](4.4.2)XDC1= L3debye⎡ ⎛ Nsubexp⎢acde⋅⎜⎢⎣⎝ 2×1016⎟⎠⎞−0.25V⋅gs−VTbsox−Vfb⎤⎥⎥⎦4-16 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Charge-Thickness Capacitance Modelwhere X DC is in the unit of cm and (V gs - V bs - vfb) / T ox has a unit of MV/cm. Themodel parameter acde is introduced for better fitting with a default value of 1. Fornumerical statbility, (4.4.2) is replaced by (4.4.3)XDC=X1−22( X0+ X0+ δxXmax)max4(4.4.3)whereX0= X max−X DC−δxand X max =L debye /3; =10 -3 T ox .(ii) X DC of inversion chargeδ x( )The inversion charge layer thichness [32] can be formulated asXDC=⎛V1+⎜⎝gsteff1.9 × 10−7+ 4Vth−vfb−2ΦB⎞⎟2Tox ⎠0.7[ cm](4.4.4)Through vfb in (4.3.30), this equation is found to be applicable to N + or P + poly-Sigates as well as other future gate materials. Figure 4-3 illustrates the universality of(4.3.30) as verified by the numerical quantum simulations, where the x-axeBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-17

Charge-Thickness Capacitance Modelrepresents the boundary conditions (the average of the electric fields at the top andthe bottom of the charge layers) of the Schrodinger and the Poisson equations.Inversion Charge Thickness (A)7060Tox=20A Tox=50ATox=70A Tox=90ASolid - Nsub=2e16cm -350Open - Nsub=2e17cm -340+ - Nsub=2e18cm -330Model2010-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0(Vgsteff+4(Vth-Vfb-2Φ f))/Tox (MV/cm)Figure 4-3. For all Tox and Nsub, modeled inversion charge thickness agrees with numericalquantum simulations.(iii) Body charge thichness in inversionIn inversion region, the body charge thickness effect is accurately modeled byincluding the deviation of the surface potential from 2 [32]Φ sΦ B( V , + 2K12Φ)⎛V⎞⎜gsteffcv , ⋅gsteffcv ox BΦ =Φ −2Φ= ln+ 1⎟δ s Bνt⎜2⎟⎝moin⋅K1oxνt ⎠(4.4.5)where the model parameter moin (defaulting to 15) is introduced for better fit todifferent technologies. The inversion channel charge density is therefore derivedasqinv,( V )= −Coxeff⋅gsteffcv−Φ δ(4.4.6)4-18 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extrinsic CapacitanceFigure 4-4 illustrates the universality of CTM model by compariing C gg of a SiON/Ta 2 O 5 /TiN gate stack structure with an equivalent T ox of 1.8nm between data,numerical quantum simulation and modeling [32].10.07.5Measured Q.M. simulation CTM18A equivalent SiO 2thicknessCgg (pF)5.02.50.0TiN60A Ta 2O 58A SiONp-Si-2 -1 0 1 2 3Vgs (V)Figure 4-4. Universality of CTM is demonstrated by modeling the Cgg of 1.8nm equivalentT ox NMOSFET with SiON/Ta 2 O 5 /TiN gate stack.4.5 Extrinsic Capacitance4.5.1 Fringing CapacitanceThe fringing capacitance consists of a bias independent outer fringingcapacitance and a bias dependent inner fringing capacitance. Only the biasindependent outer fringing capacitance is implemented. Experimentally, itis virtually impossible to separate this capacitance with the overlapcapacitance. Nonetheless, the outer fringing capacitance can betheoretically calculated by2ε⎛ toxCF ln⎜1+π ⎝ Tpoly=ox⎞⎟⎠(4.5.1)BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-19

Extrinsic Capacitancewhere t poly is equal to4×10 – 7m. CF is a model parameter.4.5.2 Overlap CapacitanceAn accurate model for the overlap capacitance is essential. This isespecially true for the drain side where the effect of the capacitance isamplified by the transistor gain. In old capacitance models this capacitanceis assumed to be bias independent. However, experimental data show thatthe overlap capacitance changes with gate to source and gate to drainbiases. In a single drain structure or the heavily doped S/D to gate overlapregion in a LDD structure the bias dependence is the result of depleting thesurface of the source and drain regions. Since the modulation is expected tobe very small, we can model this region with a constant capacitance.However in LDD MOSFETs a substantial portion of the LDD region canbe depleted, both in the vertical and lateral directions. This can lead to alarge reduction of overlap capacitance. This LDD region can be inaccumulation or depletion. We use a single equation for both regions byusing such smoothing parameters as V gs,overlap and V gd,overlap for the sourceand drain side, respectively. Unlike the case with the intrinsic capacitance,the overlap capacitances are reciprocal. In other words, C gs,overlap =C sg,overlap and C gd,overlap = C dg,overlap .(i) Source Overlap Charge(4.5.2)QW⎛+ CGS1⎜V⎜⎝CKAPPA⎛− ⎜−1+2 ⎜⎝V ⎞⎞gs overlap1−⎟⎟CKAPPA⎟⎟⎠⎠overlap s= CGS0⋅Vgsgs−Vgs,overlap4 ,active4-20 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extrinsic Capacitance2( V + δ ) 4δ⎞ ⎟,0. V1Vgs , overlap= ⎜ ⎛ Vgs+ δ1−gs 1 1 1= 022⎝+ δ⎠(4.5.3)where CKAPPA is a model parameter. CKAPPA is related to the averagedoping of LDD region byCKAPPA=2εqNsi LDD2CoxThe typical value for N LDD is 5×10 17 cm -3 .(ii) Drain Overlap ChargeQW⎛+ CGD1⎜V⎜⎝(iii) Gate Overlap Charge(4.5.4)CKAPPA ⎛− ⎜−1+2 ⎜⎝(4.5.5)V ⎞⎞gd overlap1−⎟⎟CKAPPA ⎟⎟⎠⎠overlap , d4,= CGD0⋅Vgdgd−Vgd, overlapactive2( V + δ ) 4δ⎟⎞, 0. V⎠1Vgd , overlap= ⎜ ⎛ Vgd+ δ 1 −gd 11 1 = 022 ⎝+ δQoverlap , g(4.5.6)( Q + Q + ( CGB ⋅ L ) ⋅V)= −0overlap , doverlap , sactivegbIn the above expressions, if CGS0 and CGD0 (the overlap capacitancesbetween the gate and the heavily doped source/drain regions, respectively)are not given, they are calculated according to the followingCGS0 = (DLC*C ox ) - CGS1 (if DLC is given and DLC > 0)BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-21

Extrinsic CapacitanceCGS0 = 0 (if the previously calculated CGS0 is less than 0)CGS0 = 0.6 Xj*C ox (otherwise)CGD0 = (DLC*C ox ) - CGD1 (if DLC is given and DLC > CGD1/Cox)CGD0 = 0 (if previously calculated CDG0 is less than 0)CGD0 = 0.6 Xj*C ox (otherwise).CGB0 in Eqn. (4.5.6) is a model parameter, which represents the gate-tobodyoverlap capacitance per unit channel length.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-22

CHAPTER 5: Non-Quasi Static Model5.1 Background InformationAs MOSFET’s become more performance-driven, the need for accurate predictionof circuit performance near cut-off frequency or under very rapid transientoperation becomes more essential. However, most SPICE MOSFET models arebased on Quasi-Static (QS) assumptions. In other words, the finite charging timefor the inversion layer is ignored. When these models are used with 40/60 chargepartitioning, unrealistically drain current spikes frequently occur [33]. In addition,the inability of these models to accurately simulate channel charge re-distributioncauses problems in fast switched-capacitor type circuits. Many Non-Quasi-Static(NQS) models have been published, but these models (1) assume, unrealistically,no velocity saturation and (2) are complex in their formulations with considerablesimulation time.5.2 The NQS ModelThe NQS model has been re-implemented in BSIM3v3.2 to improve thesimulation performance and accuracy. This model is based on the channel chargerelaxation time approach. A new charge partitioning scheme is used, which isphysically consistent with quasi-static CV model.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 5-1

Model Formulation5.3 Model FormulationThe channel of a MOSFET is analogous to a bias dependent RC distributedtransmission line (Figure 5-1a). In the Quasi-Static (QS) approach, the gatecapacitor node is lumped with both the external source and drain nodes (Figure 5-1b). This ignores the finite time for the channel charge to build-up. One Non-Quasi-Static (NQS) solution is to represent the channel as n transistors in series(Figure 5-1c). This model, although accurate, comes at the expense of simulationtime. The NQS model in BSIM3v3.2.2 was based on the circuit of Figure 5-1d.This Elmore equivalent circuit models channel charge build-up accurately becauseit retains the lowest frequency pole of the original RC network (Figure 5-1a). TheNQS model has two parameters as follows. The model flag, nqsMod, is now onlyan element (instance) parameter, no longer a model parameter. To turn on the NQSmodel, set nqsMod=1 in the instance statement. nqsMod defaults to zero with thismodel off.Name Function Default UnitnqsMod Instance flag for the NQS model 0 noneelm Elmore constant 5 noneTable 5-1. NQS model and instance parameters.5-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Model FormulationFigure 5-1. Quasi-Static and Non-Quasi-Static models for SPICE analysis.5.3.1 SPICE sub-circuit for NQS modelFigure 5-2 gives the RC-subcircuit of NQS model for SPICEimplementation. An additional node, Q def (t), is created to keep track of theamount of deficit/surplus channel charge necessary to reach theequilibrium based on the relaxation time approach. The bias-dependentresistance R (1/R=G tau ) can be determined from the RC time constant ( τ ).The current source i cheq (t) results from the equilibrium channel charge,Q cheq (t). The capacitor C is multiplied by a scaling factor C fact (with atypical value of1×10 – 9) to improve simulation accuracy. Q def now becomesQdef() t = V × ( 1⋅C)deffact(5.3.1)BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 5-3

Model FormulationQ defi cheq (t)C=1×C factV defRFigure 5-2. NQS sub-circuit for SPICE implementation.5.3.2 Relaxation timeThe relaxation time is modeled as two components: and . Instrong inversion region, is determined by , which, in turn, isdetermined by the Elmore resistance R elm ; in subthreshold region,dominates.τis expressed byτ τ driftτ diffτ τ driftτ diff1 1 1= +τ τ diffτ drift(5.3.2)R elm in strong inversoin is calculated from the channel resistance asRelm2effch2effL L= ≈elm⋅µ Q elm⋅µQ00cheq(5.3.3)5-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Model Formulationwhere elm is the Elmore constant of the RC channel network with atheorectical value of 5. The quasi-static (or equilibrium) channel chargeQ cheq (t), equal to Q inv of capMod=0, 1, 2 and 3, is used to approximate theactual channel charge Q ch (t).τ driftis formulated as(5.3.4)τdrift≈ Relm⋅CoxWeffLeffCoxWeffL≈elm⋅µ Q03effcheqτ diffhas the form of(5.3.5)τdiff2qL eff=16 ⋅ µ kT05.3.3 Terminal charging current and charge partitioningConsidering both the transport and charging component, the total currentrelated to the terminals D, G and S can be written as∂Qd, g,siD , G,S() t = ID,G,S( DC)+∂t() t(5.3.6)Based on the relaxation time approach, the terminal charge andcorresponding charging current can be formulated byBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 5-5

Model FormulationQdef() t = Q () t − Q () tcheqch(5.3.7)and∂Q∂Qdef∂td,g,s∂t() t ∂Q() t Q () t=cheq∂t−defτ() tQ () t= D,G,Sxpartdefτ(5.3.8a)(5.3.8b)where D,G,S xpart are the NQS channel charge partitioning number forterminals D, G and S, respectively; D xpart + S xpart = 1 and G xpart = -1. It isimportant for D xpart and S xpart to be consistent with the quasi-static chargepartitioning number XPART and to be equal (D xpart = S xpart ) at V ds =0 (whichis not the case in the previous version), where the transistor operation modechanges (between forward and reverse modes). Based on thisconsideration, D xpart is now formulated asQdD xpart = =Qd+ QsQQdcheq(5.3.9)which is now bias dependent. For example, the derivities of D xpart can beeasily obtained based on the quasi-static results:dDxpartdVi= 1Qcheq( S ⋅C−D⋅C)xpartdixpartsi(5.3.10)BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 5-6

Model Formulationwhere i represents the four terminals and C di and C si are the intrinsiccapacitances calculated from the quasi-static analysis. The correspondingvalues for S xpart can be derived from the fact that D xpart + S xpart = 1.In the accumulation and depletion regions, Eq. (5.3.9) is simplified asIf XPART < 0.5, D xpart = 0.4;Else if XPART > 0.5, D xpart = 0.0;Else D xpart = 0.5;5.3.4 Derivation of nodal conductancesThis section gives some examples of how to derive the nodal conductancesrelated to NQS for transient analysis. By noting that τ = RC, G tau can bederived asCGtau=τfact(5.3.11)τis given by Eq. (5.3.2). Based on Eq. (5.3.8b), the self-conductance dueto NQS at the transistor node D can be derived asdDdVxpartd⋅( G ⋅V)taudef+ Dxpart⋅VdefdG⋅dVtaud(5.3.12)The trans-conductance due to NQS on the node D relative to the node ofQ def can be derived asDxpart ⋅Gtau(5.3.13)BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 5-7

Model FormulationOther conductances can also be obtained in a similar way.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 5-8

CHAPTER 6: Parameter ExtractionParameter extraction is an important part of model development. Many differentextraction methods have been developed [23, 24]. The appropriate methodology dependson the model and on the way the model is used. A combination of a local optimization andthe group device extraction strategy is adopted for parameter extraction.6.1 Optimization strategyThere are two main, different optimization strategies: global optimization andlocal optimization. Global optimization relies on the explicit use of a computer tofind one set of model parameters which will best fit the available experimental(measured) data. This methodology may give the minimum average error betweenmeasured and simulated (calculated) data points, but it also treats each parameteras a "fitting" parameter. Physical parameters extracted in such a manner mightyield values that are not consistent with their physical intent.In local optimization, many parameters are extracted independently of oneanother. Parameters are extracted from device bias conditions which correspond todominant physical mechanisms. Parameters which are extracted in this mannermight not fit experimental data in all the bias conditions. Nonetheless, theseextraction methodologies are developed specifically with respect to a givenparameter’s physical meaning. If properly executed, it should, overall, predictBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-1

Extraction Strategiesdevice performance quite well. Values extracted in this manner will now havesome physical relevance.6.2 Extraction StrategiesTwo different strategies are available for extracting parameters: the single deviceextraction strategy and group device extraction strategy. In single deviceextraction strategy, experimental data from a single device is used to extract acomplete set of model parameters. This strategy will fit one device very well butwill not fit other devices with different geometries. Furthermore, single deviceextraction strategy can not guarantee that the extracted parameters are physical. Ifonly one set of channel length and width is used, parameters related to channellength and channel width dependencies can not be determined.BSIM3v3 uses group device extraction strategy. This requires measured data fromdevices with different geometries. All devices are measured under the same biasconditions. The resulting fit might not be absolutely perfect for any single devicebut will be better for the group of devices under consideration.6.3 Extraction Procedure6.3.1 Parameter Extraction RequirementsOne large size device and two sets of smaller-sized devices are needed toextract parameters, as shown in Figure 6-1.6-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction ProcedureWOrthogonal Set of W and LW minL minLarge W and LLFigure 6-1. Device geometries used for parameter extractionThe large-sized device (W ≥ 10µm, L ≥ 10µm) is used to extractparameters which are independent of short/narrow channel effects andparasitic resistance. Specifically, these are: mobility, the large-sized devicethreshold voltage V Tideal , and the body effect coefficients K 1 and K 2 whichdepend on the vertical doping concentration distribution. The set of deviceswith a fixed large channel width but different channel lengths are used toextract parameters which are related to the short channel effects. Similarly,the set of devices with a fixed, long channel length but different channelwidths are used to extract parameters which are related to narrow widthBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-3

Extraction Procedureeffects. Regardless of device geometry, each device will have to bemeasured under four, distinct bias conditions.(1) I ds vs. V gs @ V ds = 0.05V with different V bs .(2) I ds vs. V ds @ V bs = 0V with different V gs .(3) I ds vs. V gs @ V ds = V dd with different V bs . (V dd is the maximum drainvoltage).(4) I ds vs. V ds @ V bs = V bb with different V gs . (|V bb | is the maximum bodybias).6.3.2 OptimizationThe optimization process recommended is a combination of Newton-Raphson's iteration and linear-squares fit of either one, two, or threevariables. This methodology was discussed by M. C. Jeng [18]. A flowchart of this optimization process is shown in Figure 6-2. The modelequation is first arranged in a form suitable for Newton-Raphson's iterationas shown in Eq. (6.3.1):(6.3.1)( m) ( m) ( m)∂f P P P f P P P sim fP P m ∂ fsim m ∂ fsim P sim mexp ( 10, 20,30) − ( 1 , 2 , 3 ) = ∆ 1 + ∆ 2 + ∆P3∂ 1 ∂ P2∂ P3The variable f sim () is the objective function to be optimized. The variablef exp () stands for the experimental data. P 10 , P 20, and P 30 represent thedesired extracted parameter values. P(m) 1 , P2(m)and P(m) 3 representparameter values after the mth iteration.6-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction ProcedureInitial Guess ofParameters PiModel EquationsMeasured DataLinear Least SqusreFit Routine∆ P i(m+1) (m)P = P + ∆ Pi i i∆ P iP i(m)< δnoSTOPyesFigure 6-2. Optimization flow.To change Eq. (6.3.1) into a form that a linear least-squares fit routine canbe used (i.e. in a form of y = a + bx1 + cx2), both sides of the Eq. (6.3.1)are divided by ∂f sim / ∂P 1 . This gives the change in P 1 , ∆P(m) 1 , for the nextiteration such that:BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-5

Extraction Procedure( m + 1) ( m) ( m)i i iP = P + ∆P(6.3.2)where i=1, 2, 3 for this example. The (m+1) parameter values for P 2 and P 3are obtained in an identical fashion. This process is repeated until theincremental parameter change in parameter values ∆P i (m) are smaller thana pre-determined value. At this point, the parameters P 1 , P 2 , and P 3 havebeen extracted.6.3.3 Extraction RoutineBefore any model parameters can be extracted, some process parametershave to be provided. They are listed below in Table 6-1:Input Parameters NamesT oxN chTL drawnW drawnX jPhysical MeaningGate oxide thicknessDoping concentration in the channelTemperature at which the data is takenMask level channel lengthMask level channel widthJunction depthTable 6-1. Prerequisite input parameters prior to extraction process.The parameters are extracted in the following procedure. These proceduresare based on a physical understanding of the model and based on local6-6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction Procedureoptimization. (Note: Fitting Target Data refers to measurement data usedfor model extraction.)Step 1Extracted Parameters & Fitting TargetDataV th0 , K 1 , K 2Fitting Target Exp. Data: V th (V bs )Device & Experimental DataLarge Size Device (Large W & L).I ds vs. V gs @ V ds = 0.05V at Different V bsExtracted Experimental Data V th (V bs )Step 2Extracted Parameters & Fitting TargetDataµ 0 , U a , U b , U cFitting Target Exp. Data: Strong Inversionregion I ds (V gs , V bs )Devices & Experimental DataLarge Size Device (Large W & L).I ds vs. V gs @ V ds = 0.05V at Different V bsStep 3Extracted Parameters & Fitting TargetDataLint, R ds (R dsw , W, V bs )Fitting Target Exp. Data: Strong Inversionregion I ds (V gs , V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V ds = 0.05V at Different V bsBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-7

Extraction ProcedureStep 4Extracted Parameters & Fitting TargetDataWint, R ds (R dsw , W, V bs )Fitting Target Exp. Data: Strong Inversionregion I ds (V gs , V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed L& Different W).I ds vs. V gs @ V ds = 0.05V at DifferentV bsStep 5Extracted Parameters & Fitting TargetDataR dsw ,Prwb, WrDevices & Experimental DataR ds (R dsw , W, V bs )Fitting Target Exp. Data: R ds (R dsw , W,V bs )Step 6Extracted Parameters & Fitting TargetDataD vt0 , D vt1 , D vt2 , NlxOneFitting Target Exp. Data: V th (V bs , L, W)Devices & Experimental DataSet of Devices (Large and Fixed W &Different L).V th (V bs , L, W)6-8 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction ProcedureStep 7Extracted Parameters & Fitting TargetDataD vt0w , D vt1w , D vt2wOneFitting Target Exp. Data: V th (V bs , L, W)Devices & Experimental DataSet of Devices (Large and Fixed L &Different W).V th (V bs , L, W)Step 8Extracted Parameters & Fitting TargetDataK 3 , K 3b , W 0OneFitting Target Exp. Data: V th (V bs , L, W)Devices & Experimental DataSet of Devices (Large and Fixed L &Different W).V th (V bs , L, W)Step 9Extracted Parameters & Fitting TargetDataV off , Nfactor, C dsc , C dscbFitting Target Exp. Data: Subthresholdregion I ds (V gs , V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V ds = 0.05V at Different V bsStep 10Extracted Parameters & Fitting TargetDataDevices & Experimental DataBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-9

Extraction ProcedureC dscdFitting Target Exp. Data: Subthresholdregion I ds (V gs , V bs )One Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V bs = V bb at Different V dsStep 11Extracted Parameters & Fitting TargetDatadWbFitting Target Exp. Data: Strong Inversionregion I ds (V gs , V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V ds = 0.05V at Different V bsStep 12Extracted Parameters & Fitting TargetDatav sat , A 0 , A gsFitting Target Exp. Data: I sat (V gs , V bs )/WDevices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V ds @ V bs = 0V at Different V gsA 1 , A 2 (PMOS Only)Fitting Target Exp. Data V asat (V gs )Step 13Extracted Parameters & Fitting TargetDataDevices & Experimental Data6-10 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction ProcedureB0, B1Fitting Target Exp. Data: I sat (V gs , V bs )/WOne Set of Devices (Large and Fixed L &Different W).I ds vs. V ds @ V bs = 0V at Different V gsStep 14Extracted Parameters & Fitting TargetDatadWgFitting Target Exp. Data: I sat (V gs , V bs )/WDevices & Experimental DataOne Set of Devices (Large and Fixed L &Different W).I ds vs. V ds @ V bs = 0V at Different V gsStep 15Extracted Parameters & Fitting TargetDataP scbe1 , P scbe2Fitting Target Exp. Data: R out (V gs , V ds )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V ds @ V bs = 0V at Different V gsStep 16Extracted Parameters & Fitting TargetDataP clm , θ(D rout , P diblc1 , P diblc2 , L), PavgFitting Target Exp. Data: R out (V gs , V ds )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V ds @ V bs = 0V at Different V gsBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-11

Extraction ProcedureStep 17Extracted Parameters & Fitting TargetDataD rout , P dibl1c , Pdiblc2Fitting Target Exp. Data: θ(D rout ,P diblc1 , P diblc2 , L)Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).θ(D rout , P diblc1 , P diblc2 , L)Step 18Extracted Parameters & Fitting TargetDataP dibl1cbFitting Target Exp. Data: θ(D rout ,P diblc1 , P diblc2 , L, V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ fixed V gs at Different V bsStep 19Extracted Parameters & Fitting TargetDataθ dibl (Eta0, Etab, Dsub, L)Fitting Target Exp. Data: Subthresholdregion I ds (V gs , V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V ds = V dd at Different V bs6-12 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction ProcedureStep 20Extracted Parameters & Fitting TargetDataEta0, Etab, DsubFitting Target Exp. Data: θ dibl (Eta0,Etab, L)Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V ds = V dd at Different V bsStep 21Extracted Parameters & Fitting TargetDataKetaFitting Target Exp. Data: I sat (V gs , V bs )/WDevices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V ds @ V bs = V bb at Different V gsStep 22Extracted Parameters & Fitting TargetDataα 0 , α 1 , β 0Fitting Target Exp. Data: I sub (V gs , V bs )/WDevices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V ds @ V bs = V bb at Different V dsBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-13

Notes on Parameter Extraction6.4 Notes on Parameter Extraction6.4.1 Parameters with Special NotesBelow is a list of model parameters which have special notes for parameterextraction.Symbols usedin SPICEDescriptionDefaultValueUnitNotesVth0Threshold voltage for large W and L device @Vbs=0V0.7 (NMOS)-0.7 (PMOS)K1 First order body effect coefficient 0.5 V 1/2 nI-2K2 Second order body effect coefficient 0 none nI-2Vbm Maximum applied body bias -3 V nI-2Nch Channel doping concentration 1.7E17 1/cm 3 nI-3gamma1 Body-effect coefficient near interface calculated V 1/2 nI-4gamma2 Body-effect coefficient in the bulk calculated V 1/2 nI-5Vbx Vbs at which the depletion width equals xt calculated V nI-6CgsoCgdoNon-LDD source-gate overlap capacitance perchannel lengthNon-Ldd drain-gate overlap capacitance perchannel lengthVnI-1calculated F/m nC-1calculated F/m nC-2CF Fringing field capacitance calculated F/m nC-3Table 6-2. Parameters with notes for extraction.6-14 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Notes on Parameter Extraction6.4.2 Explanation of NotesnI-1. If V th0 is not specified, it is calculated byVth0= VFB+ Φs+ K1Φswhere the model parameter V FB =-1.0. If V th0 is specified, V FB defaults toVVKFB=th0−Φs−1ΦsnI-2. If K 1 and K 2 are not given, they are calculated based onK= γ2− K212Φ−sV bmK2( γ1−γ)( Φs−Vbx− Φs)Φs( Φs−Vbm− Φs) + Vbm=22whereΦ sis calculated byΦs=2Vtm0⎛ Nln⎜⎝ nich⎟ ⎞⎠Vtm 0=kBTqnomBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-15

Notes on Parameter Extractionni= 1.45 × 1010⎛ Tnom⎞⎜ ⎟⎝ 300.15 ⎠1.5⎛Eexp⎜ 21.5565981 −⎝2Vg 0tm0⎞⎟⎠Eg02nom−47.02×10 T= 1.16 −T + 1108nomwhere E g0 is the energy bandgap at temperature T nom .nI-3. If N ch is not given andγ 1is given, N ch is calculated fromNch2γ1C=2qε2oxsiIf both and N ch are not given, N ch defaults to 1.7e23 m -3 and isγ 1γ 1calculated from N ch .nI-4. Ifγ 1is not given, it is calculated byγ1 =2qεNCsioxchnI-5. Ifγ 2is not given, it is calculated byγ2=2qεNCsioxsubnI-6. If V bx is not given, it is calculated byqNchX2εsi2t= Φs−Vbx6-16 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Notes on Parameter ExtractionnC-1. If Cgso is not given, it is calculated byif (dlc is given and is greater 0),Cgso = dlc * Cox - Cgs1if (Cgso < 0)Cgso = 0else Cgso = 0.6 Xj * CoxnC-2. If Cgdo is not given, it is calculated byif (dlc is given and is greater than 0),Cgdo = dlc * Cox - Cgd1if (Cgdo < 0)Cgdo = 0else Cgdo = 0.6 Xj * CoxnC-3. If CF is not given then it is calculated usin byCF = ⎛ + × −2ε⎞⎜1 4 10 7oxln⎟π ⎝ Tox ⎠BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-17

Notes on Parameter ExtractionBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-18

CHAPTER 6: Parameter ExtractionParameter extraction is an important part of model development. Many differentextraction methods have been developed [23, 24]. The appropriate methodology dependson the model and on the way the model is used. A combination of a local optimization andthe group device extraction strategy is adopted for parameter extraction.6.1 Optimization strategyThere are two main, different optimization strategies: global optimization andlocal optimization. Global optimization relies on the explicit use of a computer tofind one set of model parameters which will best fit the available experimental(measured) data. This methodology may give the minimum average error betweenmeasured and simulated (calculated) data points, but it also treats each parameteras a "fitting" parameter. Physical parameters extracted in such a manner mightyield values that are not consistent with their physical intent.In local optimization, many parameters are extracted independently of oneanother. Parameters are extracted from device bias conditions which correspond todominant physical mechanisms. Parameters which are extracted in this mannermight not fit experimental data in all the bias conditions. Nonetheless, theseextraction methodologies are developed specifically with respect to a givenparameter’s physical meaning. If properly executed, it should, overall, predictBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-1

Extraction Strategiesdevice performance quite well. Values extracted in this manner will now havesome physical relevance.6.2 Extraction StrategiesTwo different strategies are available for extracting parameters: the single deviceextraction strategy and group device extraction strategy. In single deviceextraction strategy, experimental data from a single device is used to extract acomplete set of model parameters. This strategy will fit one device very well butwill not fit other devices with different geometries. Furthermore, single deviceextraction strategy can not guarantee that the extracted parameters are physical. Ifonly one set of channel length and width is used, parameters related to channellength and channel width dependencies can not be determined.BSIM3v3 uses group device extraction strategy. This requires measured data fromdevices with different geometries. All devices are measured under the same biasconditions. The resulting fit might not be absolutely perfect for any single devicebut will be better for the group of devices under consideration.6.3 Extraction Procedure6.3.1 Parameter Extraction RequirementsOne large size device and two sets of smaller-sized devices are needed toextract parameters, as shown in Figure 6-1.6-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction ProcedureWOrthogonal Set of W and LW minL minLarge W and LLFigure 6-1. Device geometries used for parameter extractionThe large-sized device (W ≥ 10µm, L ≥ 10µm) is used to extractparameters which are independent of short/narrow channel effects andparasitic resistance. Specifically, these are: mobility, the large-sized devicethreshold voltage V Tideal , and the body effect coefficients K 1 and K 2 whichdepend on the vertical doping concentration distribution. The set of deviceswith a fixed large channel width but different channel lengths are used toextract parameters which are related to the short channel effects. Similarly,the set of devices with a fixed, long channel length but different channelwidths are used to extract parameters which are related to narrow widthBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-3

Extraction Procedureeffects. Regardless of device geometry, each device will have to bemeasured under four, distinct bias conditions.(1) I ds vs. V gs @ V ds = 0.05V with different V bs .(2) I ds vs. V ds @ V bs = 0V with different V gs .(3) I ds vs. V gs @ V ds = V dd with different V bs . (V dd is the maximum drainvoltage).(4) I ds vs. V ds @ V bs = V bb with different V gs . (|V bb | is the maximum bodybias).6.3.2 OptimizationThe optimization process recommended is a combination of Newton-Raphson's iteration and linear-squares fit of either one, two, or threevariables. This methodology was discussed by M. C. Jeng [18]. A flowchart of this optimization process is shown in Figure 6-2. The modelequation is first arranged in a form suitable for Newton-Raphson's iterationas shown in Eq. (6.3.1):(6.3.1)( m) ( m) ( m)∂f P P P f P P P sim fP P m ∂ fsim m ∂ fsim P sim mexp ( 10, 20,30) − ( 1 , 2 , 3 ) = ∆ 1 + ∆ 2 + ∆P3∂ 1 ∂ P2∂ P3The variable f sim () is the objective function to be optimized. The variablef exp () stands for the experimental data. P 10 , P 20, and P 30 represent thedesired extracted parameter values. P(m) 1 , P2(m)and P(m) 3 representparameter values after the mth iteration.6-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction ProcedureInitial Guess ofParameters PiModel EquationsMeasured DataLinear Least SqusreFit Routine∆ P i(m+1) (m)P = P + ∆ Pi i i∆ P iP i(m)< δnoSTOPyesFigure 6-2. Optimization flow.To change Eq. (6.3.1) into a form that a linear least-squares fit routine canbe used (i.e. in a form of y = a + bx1 + cx2), both sides of the Eq. (6.3.1)are divided by ∂f sim / ∂P 1 . This gives the change in P 1 , ∆P(m) 1 , for the nextiteration such that:BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-5

Extraction Procedure( m + 1) ( m) ( m)i i iP = P + ∆P(6.3.2)where i=1, 2, 3 for this example. The (m+1) parameter values for P 2 and P 3are obtained in an identical fashion. This process is repeated until theincremental parameter change in parameter values ∆P i (m) are smaller thana pre-determined value. At this point, the parameters P 1 , P 2 , and P 3 havebeen extracted.6.3.3 Extraction RoutineBefore any model parameters can be extracted, some process parametershave to be provided. They are listed below in Table 6-1:Input Parameters NamesT oxN chTL drawnW drawnX jPhysical MeaningGate oxide thicknessDoping concentration in the channelTemperature at which the data is takenMask level channel lengthMask level channel widthJunction depthTable 6-1. Prerequisite input parameters prior to extraction process.The parameters are extracted in the following procedure. These proceduresare based on a physical understanding of the model and based on local6-6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction Procedureoptimization. (Note: Fitting Target Data refers to measurement data usedfor model extraction.)Step 1Extracted Parameters & Fitting TargetDataV th0 , K 1 , K 2Fitting Target Exp. Data: V th (V bs )Device & Experimental DataLarge Size Device (Large W & L).I ds vs. V gs @ V ds = 0.05V at Different V bsExtracted Experimental Data V th (V bs )Step 2Extracted Parameters & Fitting TargetDataµ 0 , U a , U b , U cFitting Target Exp. Data: Strong Inversionregion I ds (V gs , V bs )Devices & Experimental DataLarge Size Device (Large W & L).I ds vs. V gs @ V ds = 0.05V at Different V bsStep 3Extracted Parameters & Fitting TargetDataLint, R ds (R dsw , W, V bs )Fitting Target Exp. Data: Strong Inversionregion I ds (V gs , V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V ds = 0.05V at Different V bsBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-7

Extraction ProcedureStep 4Extracted Parameters & Fitting TargetDataWint, R ds (R dsw , W, V bs )Fitting Target Exp. Data: Strong Inversionregion I ds (V gs , V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed L& Different W).I ds vs. V gs @ V ds = 0.05V at DifferentV bsStep 5Extracted Parameters & Fitting TargetDataR dsw ,Prwb, WrDevices & Experimental DataR ds (R dsw , W, V bs )Fitting Target Exp. Data: R ds (R dsw , W,V bs )Step 6Extracted Parameters & Fitting TargetDataD vt0 , D vt1 , D vt2 , NlxOneFitting Target Exp. Data: V th (V bs , L, W)Devices & Experimental DataSet of Devices (Large and Fixed W &Different L).V th (V bs , L, W)6-8 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction ProcedureStep 7Extracted Parameters & Fitting TargetDataD vt0w , D vt1w , D vt2wOneFitting Target Exp. Data: V th (V bs , L, W)Devices & Experimental DataSet of Devices (Large and Fixed L &Different W).V th (V bs , L, W)Step 8Extracted Parameters & Fitting TargetDataK 3 , K 3b , W 0OneFitting Target Exp. Data: V th (V bs , L, W)Devices & Experimental DataSet of Devices (Large and Fixed L &Different W).V th (V bs , L, W)Step 9Extracted Parameters & Fitting TargetDataV off , Nfactor, C dsc , C dscbFitting Target Exp. Data: Subthresholdregion I ds (V gs , V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V ds = 0.05V at Different V bsStep 10Extracted Parameters & Fitting TargetDataDevices & Experimental DataBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-9

Extraction ProcedureC dscdFitting Target Exp. Data: Subthresholdregion I ds (V gs , V bs )One Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V bs = V bb at Different V dsStep 11Extracted Parameters & Fitting TargetDatadWbFitting Target Exp. Data: Strong Inversionregion I ds (V gs , V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V ds = 0.05V at Different V bsStep 12Extracted Parameters & Fitting TargetDatav sat , A 0 , A gsFitting Target Exp. Data: I sat (V gs , V bs )/WDevices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V ds @ V bs = 0V at Different V gsA 1 , A 2 (PMOS Only)Fitting Target Exp. Data V asat (V gs )Step 13Extracted Parameters & Fitting TargetDataDevices & Experimental Data6-10 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction ProcedureB0, B1Fitting Target Exp. Data: I sat (V gs , V bs )/WOne Set of Devices (Large and Fixed L &Different W).I ds vs. V ds @ V bs = 0V at Different V gsStep 14Extracted Parameters & Fitting TargetDatadWgFitting Target Exp. Data: I sat (V gs , V bs )/WDevices & Experimental DataOne Set of Devices (Large and Fixed L &Different W).I ds vs. V ds @ V bs = 0V at Different V gsStep 15Extracted Parameters & Fitting TargetDataP scbe1 , P scbe2Fitting Target Exp. Data: R out (V gs , V ds )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V ds @ V bs = 0V at Different V gsStep 16Extracted Parameters & Fitting TargetDataP clm , θ(D rout , P diblc1 , P diblc2 , L), PavgFitting Target Exp. Data: R out (V gs , V ds )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V ds @ V bs = 0V at Different V gsBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-11

Extraction ProcedureStep 17Extracted Parameters & Fitting TargetDataD rout , P dibl1c , Pdiblc2Fitting Target Exp. Data: θ(D rout ,P diblc1 , P diblc2 , L)Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).θ(D rout , P diblc1 , P diblc2 , L)Step 18Extracted Parameters & Fitting TargetDataP dibl1cbFitting Target Exp. Data: θ(D rout ,P diblc1 , P diblc2 , L, V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ fixed V gs at Different V bsStep 19Extracted Parameters & Fitting TargetDataθ dibl (Eta0, Etab, Dsub, L)Fitting Target Exp. Data: Subthresholdregion I ds (V gs , V bs )Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V ds = V dd at Different V bs6-12 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Extraction ProcedureStep 20Extracted Parameters & Fitting TargetDataEta0, Etab, DsubFitting Target Exp. Data: θ dibl (Eta0,Etab, L)Devices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V gs @ V ds = V dd at Different V bsStep 21Extracted Parameters & Fitting TargetDataKetaFitting Target Exp. Data: I sat (V gs , V bs )/WDevices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V ds @ V bs = V bb at Different V gsStep 22Extracted Parameters & Fitting TargetDataα 0 , α 1 , β 0Fitting Target Exp. Data: I sub (V gs , V bs )/WDevices & Experimental DataOne Set of Devices (Large and Fixed W &Different L).I ds vs. V ds @ V bs = V bb at Different V dsBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-13

Notes on Parameter Extraction6.4 Notes on Parameter Extraction6.4.1 Parameters with Special NotesBelow is a list of model parameters which have special notes for parameterextraction.Symbols usedin SPICEDescriptionDefaultValueUnitNotesVth0Threshold voltage for large W and L device @Vbs=0V0.7 (NMOS)-0.7 (PMOS)K1 First order body effect coefficient 0.5 V 1/2 nI-2K2 Second order body effect coefficient 0 none nI-2Vbm Maximum applied body bias -3 V nI-2Nch Channel doping concentration 1.7E17 1/cm 3 nI-3gamma1 Body-effect coefficient near interface calculated V 1/2 nI-4gamma2 Body-effect coefficient in the bulk calculated V 1/2 nI-5Vbx Vbs at which the depletion width equals xt calculated V nI-6CgsoCgdoNon-LDD source-gate overlap capacitance perchannel lengthNon-Ldd drain-gate overlap capacitance perchannel lengthVnI-1calculated F/m nC-1calculated F/m nC-2CF Fringing field capacitance calculated F/m nC-3Table 6-2. Parameters with notes for extraction.6-14 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Notes on Parameter Extraction6.4.2 Explanation of NotesnI-1. If V th0 is not specified, it is calculated byVth0= VFB+ Φs+ K1Φswhere the model parameter V FB =-1.0. If V th0 is specified, V FB defaults toVVKFB=th0−Φs−1ΦsnI-2. If K 1 and K 2 are not given, they are calculated based onK= γ2− K212Φ−sV bmK2( γ1−γ)( Φs−Vbx− Φs)Φs( Φs−Vbm− Φs) + Vbm=22whereΦ sis calculated byΦs=2Vtm0⎛ Nln⎜⎝ nich⎟ ⎞⎠Vtm 0=kBTqnomBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-15

Notes on Parameter Extractionni= 1.45 × 1010⎛ Tnom⎞⎜ ⎟⎝ 300.15 ⎠1.5⎛Eexp⎜ 21.5565981 −⎝2Vg 0tm0⎞⎟⎠Eg02nom−47.02×10 T= 1.16 −T + 1108nomwhere E g0 is the energy bandgap at temperature T nom .nI-3. If N ch is not given andγ 1is given, N ch is calculated fromNch2γ1C=2qε2oxsiIf both and N ch are not given, N ch defaults to 1.7e23 m -3 and isγ 1γ 1calculated from N ch .nI-4. Ifγ 1is not given, it is calculated byγ1 =2qεNCsioxchnI-5. Ifγ 2is not given, it is calculated byγ2=2qεNCsioxsubnI-6. If V bx is not given, it is calculated byqNchX2εsi2t= Φs−Vbx6-16 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Notes on Parameter ExtractionnC-1. If Cgso is not given, it is calculated byif (dlc is given and is greater 0),Cgso = dlc * Cox - Cgs1if (Cgso < 0)Cgso = 0else Cgso = 0.6 Xj * CoxnC-2. If Cgdo is not given, it is calculated byif (dlc is given and is greater than 0),Cgdo = dlc * Cox - Cgd1if (Cgdo < 0)Cgdo = 0else Cgdo = 0.6 Xj * CoxnC-3. If CF is not given then it is calculated usin byCF = ⎛ + × −2ε⎞⎜1 4 10 7oxln⎟π ⎝ Tox ⎠BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-17

Notes on Parameter ExtractionBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 6-18

CHAPTER 7: Benchmark Test ResultsA series of benchmark tests [26] have been performed to check the model robustness,accuracy and performance. Although not all the benchmark test results are included in thischapter, the most important ones are demonstrated.7.1 Benchmark Test TypesTable 7-1 lists the various benchmark test conditions and associated figure numberincluded in this section. Notice that for each plot, smooth transitions are apparentfor current, transconductance, and source to drain resistance for all transitionregions regardless of bias conditions.Device Size Bias Conditions NotesFigureNumberW/L=20/5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Log scale 7-1W/L=20/5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Linear scale 7-2W/L=20/0.5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Log scale 7-3W/L=20/0.5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Linear scale 7-4W/L=20/5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Log scale 7-5W/L=20/5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V; W/L=20/5Linear scale 7-6W/L=20/0.5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Log scale 7-7W/L=20/0.5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Linear scale 7-8W/L=20/5 Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Vbs=0V Linear scale 7-9BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 7-1

Benchmark Test ResultsDevice Size Bias Conditions NotesFigureNumberW/L=20/0.5 Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Vbs=0V Linear scale 7-10W/L=20/5 Gm/Ids vs. Vgs @ Vds=0.05V; Vbs=0V to - Linear scale 7-113.3VW/L=20/0.5 Gm/Ids vs. Vgs @ Vds=0.05V; Vbs=0V to - Linear scale 7-123.3VW/L=20/0.5 Ids vs. Vds @Vbs=0V; Vgs=0.5V, 0.55V, 0.6V Linear scale 7-13W/L=20/5 Ids vs. Vds @Vbs=0V; Vgs=1.15V to 3.3V Linear scale 7-14W/L=20/0.5 Ids vs. Vds @Vbs=0V; Vgs=1.084V to 3.3V Linear scale 7-15W/L=20/0.5 Rout vs. Vds @ Vbs=0V; Vgs=1.084V to 3.3V Linear scale 7-16Table 7-1. Benchmark test information.7.2 Benchmark Test ResultsAll of the figures listed in Table 7-1 are shown below. Unless otherwise indicated,symbols represent measurement data and lines represent the results of the model.All of these plots serve to demonstrate the robustness and continuous behavior ofthe unified model expression for not only I ds but G m , G m /I ds , and R out as well.7-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Benchmark Test ResultsIds (A)1.E-021.E-031.E-041.E-051.E-061.E-071.E-081.E-091.E-101.E-111.E-12Vds=3.3VVds=0.05VSolid lines: Model resultsSymbols: Exp.dataW/L=20/5Tox=9 nmVbs=0V0.0 1.0 2.0 3.0 4.0Vgs (V)Figure 7-1. Continuity from subthreshold to strong inversion (log scale).Ids (A)1.8E-031.6E-031.4E-031.2E-031.0E-038.0E-046.0E-044.0E-042.0E-040.0E+00Solid lines: Model resultSymbols: Exp.dataW/L=20/5Tox=9 nmVbs=0VVds=3.3V0.0 1.0 2.0 3.0 4.0Vgs (V)Vds=0.05VFigure 7-2. Continuity from subthreshold to strong inversion (linear scale).BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 7-3

Benchmark Test ResultsIds (A)1.0E+001.0E-011.0E-021.0E-031.0E-041.0E-051.0E-061.0E-071.0E-081.0E-091.0E-101.0E-111.0E-12Vds=3.3VSolid lines: Model resultsSymbols: Exp. dataW/L=20/0.5Tox=9 nmVbs=0VVds=0.05V0.0 1.0 2.0 3.0 4.0Vgs (V)Figure 7-3. Same as Figure 7-1 but for a short channel device.Ids (A)1.0E-029.0E-038.0E-037.0E-036.0E-035.0E-034.0E-033.0E-032.0E-031.0E-030.0E+00Solid lines: Model resultsSymbols: Exp. dataW/L=20/0.5Tox=9 nmVbs=0VVds=3.3VVds=0.05V0.0 1.0 2.0 3.0 4.0Vgs (V)Figure 7-4. Same as Figure 7-2 but for a short channel device.7-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Benchmark Test ResultsIds (A)1.E-031.E-041.E-051.E-061.E-071.E-081.E-091.E-101.E-111.E-12Vbs=0VVbs=-3.3VSolid lines: Model resultsSymbols: Exp. dataW/L=20/5Tox=9 nmVds=0.05V0.0 1.0 2.0 3.0 4.0Vgs (V)Figure 7-5. Subthreshold to strong inversion continuity as a function of V bs .Ids (A)7.E-056.E-055.E-054.E-053.E-052.E-051.E-05Solid lines: Model resultsSymbols: Exp. dataW/L=20/5Tox=9 nmVds=0.05VVbs=0VVbs=-3.3V0.E+000.0 1.0 2.0 3.0 4.0Vgs (V)Figure 7-6. Subthreshold to strong inversion continuity as a function of V bs .BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 7-5

Benchmark Test ResultsIds (A)1.E-031.E-041.E-051.E-061.E-071.E-081.E-091.E-101.E-111.E-12Vbs=0VVbs=-3.3VSolid lines: Model resultsSymbols: Exp. dataW/L=20/0.5Tox=9 nmVds=0.05V0.0 1.0 2.0 3.0 4.0Vgs (V)Figure 7-7. Same as Figure 7-5 but for a short channel device.Ids (A)5.E-045.E-044.E-044.E-043.E-043.E-042.E-042.E-041.E-045.E-050.E+00W/L=20/0.5Tox=9 nmVds=0.05VVbs=0VVbs=-3.3V0.0 1.0 2.0 3.0 4.0Vgs (V)Figure 7-8. Same as Figure 7-6 but for a short channel device.7-6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Benchmark Test Resultsgm/Ids (mho/A)3025201510Vds=3.3VSolid lines: Model resultsSymbols: Exp. dataW/L=20/5Tox=9 nmVbs=0V50Vds=0.05V0.0 1.0 2.0 3.0 4.0Vgs (V)Figure 7-9. G m /I ds continuity from subthreshold to strong inversion regions.30gm/Ids (mho/A)252015105Vds=3.3VVds=0.05VW/L=20/0.5Tox=9 nmVbs=0V00.0 1.0 2.0 3.0 4.0Vgs (V)Figure 7-10. Same as Figure 7-9 but for a short channel device.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 7-7

Benchmark Test Resultsgm/Ids (mho/A)353025201510Solid lines: Model resultsSymbols: Exp. dataW/L=20/5Tox=9 nmVds=0.05VVbs=-3.3V50Vbs=0V0.0 1.0 2.0 3.0 4.0Vgs(V)Figure 7-11. G m /I ds continuity as a function of V bs .Gm/Id3530252015Solid lines: Model resultsSymbols: Exp. dataW/L=20/0.5Tox=9 nmVds=0.05V1050Vbs=0VVbs=-1.98V0.0 1.0 2.0 3.0 4.0Vgs (V)Figure 7-12. Same as Figure 7-11 but for a short channel device.7-8 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Benchmark Test ResultsIds (A)8.E-057.E-056.E-055.E-054.E-053.E-05Solid lines:BSIM3v3Dotted lines:BSIM3v2W/L=20/0.5Vgs =0.6V2.E-051.E-050.E+00Vgs=0.55VVgs=0.5V0.0 0.2 0.4 0.6 0.8Vds (V)Figure 7-13. Comparison of G ds with BSIM3v2.Ids (A)1.6E-031.4E-031.2E-031.0E-038.0E-046.0E-044.0E-04W/L=20/5Tox=9 nmVbs=0VVgs=3.3V2.0E-040.0E+00Vgs=1.15V0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5Vds (V)Figure 7-14. Smooth transitions from linear to saturation regimes.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 7-9

Benchmark Test ResultsIds (A)9.E-038.E-037.E-036.E-035.E-034.E-033.E-032.E-031.E-030.E+00W/L=20/0.5Tox=9nmVbs=0VVgs=3.3VVgs=1.084V0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5Vds (V)Figure 7-15. Same as Figure 7-14 but for a short channel device.Rout (Ohm)2.0E+051.8E+051.6E+051.4E+051.2E+051.0E+058.0E+046.0E+044.0E+042.0E+040.0E+00W/L=20/0.5Tox=9 nmVbs=0VVgs=1.084VVgs=3.3V0.0 1.0 2.0 3.0 4.0Vds (V)Figure 7-16. Continuous and non-negative R out behavior.7-10 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

CHAPTER 8: Noise Modeling8.1 Flicker NoiseSymbolsused inequation8.1.1 ParametersThere exist two models for flicker noise modeling. One is called SPICE2flicker noise model; the other is BSIM3 flicker noise model [35-36]. Theflicker noise model parameters are listed in Table 8-1.Symbolsused inSPICEDescription Default UnitNoia noia Noise parameter A (NMOS) 1e20 none(PMOS) 9.9e18Noib noib Noise parameter B (NMOS) 5e4 none(PMOS) 2.4e3Noic noic Noise parameter C (NMOS) -1.4e-12 none(PMOS) 1.4e-12Em em Saturation field 4.1e7 V/mAf af Flick noise exponent 1 noneEf ef Flicker noise frequency1 noneexponentKf kf Flicker noise coefficient 0 noneTable 8-1. Flicker noise model parameters.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 8-1

Flicker Noise8.1.2 Formulations1. For SPICE2 modeloxeffafdsKfINoise density=2C L fef(8.1)where f is the frequency.2. For BSIM3 modelIf V gs > V th + 0.12q kTµNoise density=C L fV+W2ox efftm ds2eff⋅ LeffeffefIds⎛ ⎛⎜N0+ 2 × 10Noia⋅log⎜8⋅10⎝ ⎝ Nl+ 2 × 10I ∆Lclmef 8f ⋅10Noia + Noib⋅Nl⋅1414( N + 2 × 1014 ) 2l+ Noic⋅N⎞⎟+ Noib⋅⎠2l(8.2)Noic 2 2( N0− Nl) + ( N0− Nl)2⎞⎟⎠where V tm is the thermal voltage, µ eff is the effective mobiity at the givenbias condition, and L eff and W eff are the effective channel length and width,respectively. The parameter N 0 is the charge density at the source sidegiven byN0C=ox( V −V)gsqth(8.3)The parameter N l is the charge density at the drain end given by8-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Flicker NoiseNlC=ox( V −V− min( V , V ))gsthqdsdsat(8.4)∆L clm is the channel length reduction due to channel length modulation andgiven by⎧ ⎛V⎪ ⎜⎪Litl⋅log⎜∆Lclm= ⎨ ⎜⎪⎝⎪⎩02×vsatEsat=µeffds−VLitlE( otherwise)dsatsat+ Em⎞⎟⎟⎟⎠(8.5)( forV> V )dsdsatwhereLitl 3X j T ox= wiOtherwiseSNoise density=Slimitlimit× S+ Swi(8.6)Where, S limit is the flicker noise calculated at V gs = V th + 0.1 and S wi is givenbyBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 8-3

Channel Thermal NoiseSNoia⋅Vtmwi=efWeffLeff⋅ f2ds⋅ I⋅4×1036(8.7)8.2 Channel Thermal NoiseThere also exist two models for channel thermal noise modeling. One is calledSPICE2 thermal noise model. The other is BSIM3v3 thermal noise model. Each ofthese can be toggled through the model flag, noiMod.1. For SPICE2 thermal noise model8kBT3( G + G + G )mbswhere G m , G mbs and G ds are the transconductances.2. For BSIM3v3 thermal noise model [37]m4 k TµB eff2effLQinvds(8.8)(8.9)Q inv is the inversion channel charge computed from the capacitance models(capMod = 0, 1, 2 or 3).8-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Noise Model Flag8.3 Noise Model FlagA model flag, noiMod, is used to select different combination of flicker andthermal noise models discussed above with possible optoins described in Table 8-2.noimodflag Flicker noise modelThermal noisemodel1 SPICE2 SPICE22 BSIM3v3 BSIM3v33 BSIM3v3 SPICE24 SPICE2 BSIM3v3Table 8-2. noiMod flag for differnet noise models.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 8-5

Noise Model FlagBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 8-6

CHAPTER 9: MOS Diode Modeling9.1 Diode IV ModelThe diode IV modeling now supports a resistance-free diode model and a currentlimitingfeature by introducing a new model parameter ijth (defaulting to 0.1A). Ifijth is explicitly specified to be zero, a resistance-free diode model will betriggered; otherwise two critical junction votages Vjsm for S/B diode and Vjdm forD/B diode will be computed from the value of ijth.9.1.1 Modeling the S/B DiodeIf the S/B saturation current I sbs is larger than zero, the following equationsis used to calculate the S/B diode current I bs .Case 1 - ijth is equal to zero: A resistance-free diode.Ibs= I⎛⎜⎝⎛⎜⎝V⎞⎟⎠⎞⎟⎠bssbsexp 1 +⎜ ⎜−NV ⎟tmGVmin bs(9.1)whereNV tm= NJ ⋅ KbT q⁄; NJ is a model parameter, known as the junctionemission coefficient.Case 2 - ijth is non-zero: Current limiting feature.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 9-1

Diode IV ModelIf V bs < VjsmIbs= I⎛⎜⎝⎛⎜⎝V⎞⎟⎠⎞⎟⎠bssbs⎜exp⎜−1+NV ⎟tmGminVbs(9.2)otherwiseIbsijth+I= ijth+NVtmsbs( Vbs−Vjsm) + GminVbs(9.3)with Vjsm computed by⎛ ijth ⎞Vjsm = NV⎜⎟tmln + 1⎝ Isbs⎠The saturation current I sbs is given byI = A J + P Jsbssssssw(9.4)where J s is the junction saturation current density, A S is the source junctionarea, J ssw is the sidewall junction saturation current density, P s is theperimeter of the source junction. J s and J ssw are functions of temperatureand can be written asJs= Js0⎛ E⎜⎜ Vexp⎜⎜⎝g0tm0E−Vgtm⎛ T+ XTIln⎜⎝TNJnom⎞ ⎞⎟⎟⎠ ⎟⎟⎟⎠(9.5)9-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Diode IV ModelJssw= Js0sw⎛ E⎜⎜ Vexp⎜⎜⎝g0tm0E−Vgtm⎛ T+ XTIln⎜⎝TNJnom⎞ ⎞⎟⎟⎠ ⎟⎟⎟⎠(9.6)The energy band-gap E g0 and E g at the nominal and operating temperaturesare expressed by (9.7a) and (9.7b), repectively:Eg 02nom−47.02 × 10 T= 1.16 −T + 1108nom(9.7a)E g= 1.16 −−47.02 × 10 TT + 11082(9.7b)In the above derivatoins, J s0 is the saturation current density at T nom . If J s0 isnot given,J s0= 1×10 – 4at T nom , with a default value of zero.If I sbs is not positive, I bs is calculated byA/m 2 . J s0sw is the sidewall saturation current densityIbs= G min⋅V bs(9.8)9.1.2 Modeling the D/B DiodeIf the D/B saturation current I sbd is larger than zero, the following equationsis used to calculate the D/B diode current I bd .Case 1 - ijth is equal to zero: A resistance-free diode.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 9-3

Diode IV Model(9.9)Ibd= I⎛⎜⎝⎛⎜⎝V⎞⎟⎠⎞⎟⎠bdsbdexp 1 +⎜ ⎜−NV ⎟tmGminVbdCase 2 - ijth is non-zero: Current limiting feature.If V bd < Vjdm(9.10)otherwiseIbd= I⎛⎜⎝⎛⎜⎝V⎞⎟⎠⎞⎟⎠bdsbd⎜exp ⎜−1+NV⎟tmGminVbdIbdijth + I= ijth +NVtmsbd( Vbd−Vjdm) + GminVbd(9.11)with Vjdm computed by⎛ ijth ⎞Vjdm = NV ln⎜ + 1⎟tm⎝ Isbd⎠The saturation current I sbd is given by(9.12)I = A J + PsbddsdJsswwhere A d is the drain junction area and P d is the perimeter of the drainjunction. If I sbd is not positive, I bd is calculated by(9.13)Ibd= G min⋅V bdBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 9-4

MOS Diode Capacitance Model9.1.3 Model Parameter ListsThe diode DC model parameters are listed in Table 9-1.Symbolsused inequationSymbolsused inSPICEDescription Default UnitJs0 js Saturation current density 1e-4 A/m 2Js0sw jssw Side wall saturation current density 0 A/mNJ nj Emission coefficient 1 noneXTI xti Junction current temperature exponent3.0 nonecoefficientijth ijth Limiting current 0.1 ATable 9-1. MOS diode model parameters.9.2 MOS Diode Capacitance ModelSource and drain junction capacitance can be divided into two components:the junction bottom area capacitance C jb and the junction peripherycapacitance C jp . The formula for both the capacitances is similar, but withdifferent model parameters. The equation of C jb includes the parameterssuch as C j , M j , and P b . The equation of C jp includes the parameters such asC jsw , M jsw , P bsw , C jswg , M jswg , and P bswg .9.2.1 S/B Junction CapacitanceThe S/B junction capacitance can be calculated byIf P s > W eff(9.14)sjbs( Ps−Weff) CjbsswWeffCjbsswgCapbs = A C ++BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 9-5

MOS Diode Capacitance ModelOtherwise(9.15)Capbs = A C + P Csjbssjbsswgwhere C jbs is the unit bottom area capacitance of the S/B junction,C jbssw is the periphery capacitance of the S/B junction along thefield oxide side, and C jbsswg is the periphery capacitance of the S/Bjunction along the gate oxide side.If C j is larger than zero, C jbs is calculated byif V bs < 0(9.16)Cjbs⎛ V ⎞bsCj⎜ −P⎟⎝ b ⎠−M j= 1⎟ ⎟ ⎠otherwise(9.17)⎛C ⎜jbsCj1 + M⎝V=bsjPb⎞If C jsw is large than zero, C jbssw is calculated byif V bs < 09-6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

MOS Diode Capacitance Model(9.18)CjbsswCjsw⎛ V⎜ −⎝ Pbsbsw⎞⎟⎠−M jsw= 1⎟ ⎟ ⎠otherwise(9.19)⎛C ⎜jbsswCjsw1 + M⎝V=bsjswPbsw⎞If C jswg is larger than zero, C jbsswg is calculated byif V bs < 0(9.20)CjbsswgCjswg⎛⎜V −⎝ Pbsbswg−⎞⎟⎠M jswg= 1⎟ ⎟ ⎠otherwise(9.21)⎛C ⎜jbsswgCjswg1 + M⎝V=bsjswgPbswg⎞9.2.2 D/B Junction CapacitanceThe D/B junction capacitance can be calculated byBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 9-7

MOS Diode Capacitance ModelIf P d > W eff(9.22)djbd( Pd−Weff) CjbdswWeffCjbdswgCapbd = A C ++Otherwise(9.23)Capbd = A C + P Cdjbddjbdswgwhere C jbd is the unit bottom area capacitance of the D/B junction,C jbdsw is the periphery capacitance of the D/B junction along thefield oxide side, and C jbdswg is the periphery capacitance of the D/Bjunction along the gate oxide side.If C j is larger than zero, C jbd is calculated byif V bd < 0(9.24)Cjbd⎛ V ⎞bdCj⎜ −P⎟⎝ b ⎠−M j= 1⎟ ⎟ ⎠otherwise(9.25)⎛ VC ⎜jbdCj1 + M⎝=bdjPb⎞If C jsw is large than zero, C jbdsw is calculated byif V bd < 09-8 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

MOS Diode Capacitance Model(9.26)CjbdswCjsw⎛ V⎜ −⎝ Pbdbsw⎞⎟⎠−M jsw= 1⎟ ⎟ ⎠otherwise(9.27)⎛C ⎜jbdswCjsw1 + M⎝V=bdjswPbsw⎞If C jswg is larger than zero, C jbdswg is calculated byif V bd < 0(9.28)CjbdswgCjswg⎛⎜V −⎝ Pbdbswg−⎞⎟⎠M jswg= 1⎟ ⎟ ⎠otherwise(9.29)⎛C ⎜jbdswgCjswg1 + M⎝V=bdjswgPbswg⎞BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 9-9

MOS Diode Capacitance Model9.2.3 Temperature Dependence of Junction CapacitanceThe temperature dependence of the junction capacitance is modeled.Both zero-bias unit-area junction capacitance (C j , C jsw andC jswg ) and built-in potential of the junction (P b , P bsw and P bswg ) aretemperature dependent and modeled in the following.For zero-bias junction capacitance:CCjswj( T ) = C ( T ) ⋅ ( 1+tcj ⋅ ∆T)jnom( T ) = C ( T ) ⋅( 1+tcjsw⋅∆T)jswnom(9.30a)(9.30b)Cjswg( T ) = C ( T ) ⋅( 1+tcjswg ⋅ ∆T)jswgnom(9.30c)For the built-in potential:PPbswb( T ) = P ( T ) − tpb⋅∆Tbnom( T) = P ( T ) −tpbsw⋅∆Tbswnom(9.31a)(9.31b)Pbswg( T) = P ( T ) −tpbswg⋅∆Tbswgnom(9.31c)In Eqs. (9.30) and (9.31), the temperature difference is defined as9-10 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

MOS Diode Capacitance Model(9.32)∆T= T −T nomThe six new model parameters in the above equations are describedin Table 9-2.9.2.4 Junction Capacitance ParametersThe following table give a full description of those model parametersused in the diode junction capacitance modeling.Symbolsused inequationSymbolsused inSPICECj cj Bottom junction capacitance perunit area at zero biasDescription Default Unit5e-4 F/m 2Mj mj Bottom junction capacitance grading0.5 nonecoefficientPb pb Bottom junction built-in potential 1.0 VCjsw cjsw Source/drain sidewall junctioncapacitance per unit length at zerobias5e-10 F/mMjsw mjsw Source/drain sidewall junctioncapacitance grading coefficientPbsw pbsw Source/drain side wall junctionbuilt-in potentialCjswg cjswg Source/drain gate side wall junctioncapacitance per unit length atzero biasMjswg mjswg Source/drain gate side wall junctioncapacitance grading coefficient0.33 none1.0 VCjswMjswPbswg pbswg Source/drain gate side wall junctionPbswVbuilt-in potentialtpb tpb Temperature coefficient of Pb 0.0 V/Ktpbsw tpbsw Temperature coefficient of Pbsw 0.0 V/KF/mnoneBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 9-11

MOS Diode Capacitance ModelSymbolsused inequationSymbolsused inSPICEDescription Default Unittpbswg tpbswg Temperature coefficient of Pbswg 0.0 V/Ktcj tcj Temperature coefficient of Cj 0.0 1/Ktcjsw tcjsw Temperature coefficient of Cjsw 0.0 1/Ktcjswg tcjswg Temperature coefficient of Cjswg 0.0 1/KTable 9-2. MOS Junction Capacitance Model Parameters.9-12 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

APPENDIX A: Parameter ListA.1 Model Control ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteNone level The model selector 8 noneNone version Model version selector 3.2 noneNone binUnit Bining unit selector 1 noneNone param- Parameter value check False noneChkmobMod mobMod Mobility model selector 1 nonecapMod capMod Flag for capacitance models 3 nonenqsMod a nqsMod Flag for NQS model 0 nonenoiMod noiMod Flag for noise models 1 nonea. nqsMod is now an element (instance) parameter, no longer a modelparameter.A.2 DC ParametersBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-1

DC ParametersSymbolsused inequationSymbolsused inSPICEVth0 vth0 Threshold voltage @Vbs=0 forLarge L.Description Default Unit Note0.7(NMOS)-0.7(PMOS)VFB vfb Flat-band voltage Calculated V nI-1K1 k1 First order body effect coefficient0.5 V 1/2 nI-2K2 k2 Second order body effect coefficient0.0 none nI-2K3 k3 Narrow width coefficient 80.0 noneK3b k3b Body effect coefficient of k3 0.0 1/VW0 w0 Narrow width parameter 2.5e-6 mNlx nlx Lateral non-uniform doping 1.74e-7 mparameterVbm vbm Maximum applied body bias in -3.0 VVth calculationDvt0 dvt0 first coefficient of short-channeleffect on Vth2.2 noneDvt1 dvt1 Second coefficient of shortchanneleffect on VthDvt2 dvt2 Body-bias coefficient of shortchanneleffect on VthDvt0w dvt0w First coefficient of narrowwidth effect on Vth for smallchannel lengthDvt1w dvtw1 Second coefficient of narrowwidth effect on Vth for smallchannel lengthV0.53 none-0.032 1/V0 1/m5.3e6 1/mnI-1A-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

DC ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteDvt2w dvt2w Body-bias coefficient of narrowwidth effect for small channellengthµ0 u0 Mobility at Temp = TnomNMOSFETPMOSFETUa ua First-order mobility degradationcoefficientUb ub Second-order mobility degradationcoefficientUc uc Body-effect of mobility degradationcoefficient-0.032 1/V670.0250.02.25E-9cm 2 /Vsm/V5.87E-19 (m/V) 2mobMod=1, 2:-4.65e-11mobMod=3:-0.046m/V 21/Vνsat vsat Saturation velocity at Temp =TnomA0 a0 Bulk charge effect coefficientfor channel length8.0E4 m/sec1.0 noneAgs ags gate bias coefficient of Abulk 0.0 1/VB0 b0 Bulk charge effect coefficientfor channel width0.0 mB1 b1 Bulk charge effect width offset 0.0 mKeta keta Body-bias coefficient of bulk -0.047 1/Vcharge effectA1 a1 First non-saturation effect0.0 1/VparameterA2 a2 Second non-saturation factor 1.0 noneBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-3

DC ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteRdsw rdsw Parasitic resistance per unitwidth0.0 Ω-µm WrPrwb prwb Body effect coefficient of Rdsw 0 V -1/2Prwg prwg Gate bias effect coefficient ofRdswWr wr Width Offset from Weff forRds calculationWint wint Width offset fitting parameterfrom I-V without biasLint lint Length offset fitting parameterfrom I-V without biasdWg dwg Coefficient of Weff’s gatedependencedWb dwb Coefficient of Weff’s substratebody bias dependenceVoff voff Offset voltage in the subthresholdregion at large W and L0 1/V1.0 none0.0 m0.0 m0.0 m/V0.0 m/V 1/2-0.08 VNfactor nfactor Subthreshold swing factor 1.0 noneEta0 eta0 DIBL coefficient in subthresholdregion0.08 noneEtab etab Body-bias coefficient for the -0.07 1/Vsubthreshold DIBL effectDsub dsub DIBL coefficient exponent in drout nonesubthreshold regionCit cit Interface trap capacitance 0.0 F/m 2Cdsc cdsc Drain/Source to channel couplingcapacitance2.4E-4 F/m 2A-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

DC ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteCdscb cdscb Body-bias sensitivity of Cdsc 0.0 F/Vm 2Cdscd cdscd Drain-bias sensitivity of Cdsc 0.0 F/Vm 2Pclm pclm Channel length modulationparameterPdiblc1 pdiblc1 First output resistance DIBLeffect correction parameterPdiblc2 pdiblc2 Second output resistance DIBLeffect correction parameterPdiblcb pdiblcb Body effect coefficient ofDIBL correction parametersDrout drout L dependence coefficient of theDIBL correction parameter inRoutPscbe1 pscbe1 First substrate current bodyeffectparameterPscbe2 pscbe2 Second substrate current bodyeffectparameterPvag pvag Gate dependence of Early voltage1.3 none0.39 none0.0086 none0 1/V0.56 none4.24E8 V/m1.0E-5 m/V nI-30.0 noneδ delta Effective Vds parameter 0.01 VNgate ngate poly gate doping concentration 0 cm -3α0 alpha0 The first parameter of impactionization currentα1 alpha1 Isub parameter for length scalingβ0 beta0 The second parameter of impactionization current0 m/V0.0 1/V30 VBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-5

C-V Model ParametersSymbolsused inequationSymbolsused inSPICERsh rsh Source drain sheet resistance inohm per squareJs0sw jssw Side wall saturation currentdensityJs0 js Source drain junction saturationcurrent per unit areaDescription Default Unit Note0.0 Ω/square0.0 A/m1.0E-4 A/m 2ijth ijth Diode limiting current 0.1 A nI-3A.3 C-V Model ParametersSymbolsused inequationSymbolsused inSPICEDescriptionDefault Unit NoteXpart xpart Charge partitioning flag 0.0 noneCGS0 cgso Non LDD region source-gateoverlap capacitance perchannel lengthCGD0 cgdo Non LDD region drain-gateoverlap capacitance perchannel lengthCGB0 cgbo Gate bulk overlap capacitanceper unit channel lengthCj cj Bottom junction capacitanceper unit area at zero biascalculated F/m nC-1calculated F/m nC-20.0 F/m5.0e-4 F/m 2A-6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

C-V Model ParametersSymbolsused inequationSymbolsused inSPICEDescriptionMj mj Bottom junction capacitancegrating coefficientMjsw mjsw Source/Drain side wall junctioncapacitance grading coefficientCjsw cjsw Source/Drain side wall junctioncapacitance per unit areaCjswg cjswg Source/drain gate side walljunction capacitance gradingcoefficientMjswg mjswg Source/drain gate side walljunction capacitance gradingcoefficientDefault Unit Note0.50.33 none5.E-10CjswMjswF/mF/mnonePbsw pbsw Source/drain side wall junction1.0 Vbuilt-in potentialPb pb Bottom built-in potential 1.0 VPbswg pbswg Source/Drain gate side wall Pbsw Vjunction built-in potentialCGS1 cgs1 Light doped source-gate 0.0 F/mregion overlap capacitanceCGD1 cgd1 Light doped drain-gate region 0.0 F/moverlap capacitanceCKAPPA ckappa Coefficient for lightly dopedregion overlapcapacitance Fringing fieldcapacitance0.6 VCf cf fringing field capacitance calculated F/m nC-3CLC clc Constant term for the short 0.1E-6 mchannel modelCLE cle Exponential term for the shortchannel model0.6 noneBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-7

NQS ParametersSymbolsused inequationSymbolsused inSPICEDescriptionDLC dlc Length offset fitting parameterfrom C-VDWC dwc Width offset fitting parameterfrom C-VVfbcv vfbcv Flat-band voltage parameter(for capMod=0 only)noff noff CV parameter in Vgsteff,CVfor weak to strong inversionvoffcv voffcv CV parameter in Vgsteff,CVfor week to strong inversionacde acde Exponential coefficient forcharge thickness in capMod=3for accumulation and depletionregionsmoin moin Coefficient for the gate-biasdependent surface potentialDefault Unit Notelint mwint m-1 V1.0 none nC-40.0 V nC-41.0 m/V nC-415.0 none nC-4A.4 NQS ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteElm elm Elmore constant of the channel 5 noneA-8 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

dW and dL ParametersA.5 dW and dL ParametersSymbolsused inequationSymbolsused inSPICEWl wl Coefficient of length dependencefor width offsetDescription Default Unit Note0.0 m WlnWln wln Power of length dependence ofwidth offsetWw ww Coefficient of width dependencefor width offsetWwn wwn Power of width dependence ofwidth offsetWwl wwl Coefficient of length and widthcross term for width offsetLl ll Coefficient of length dependencefor length offsetLln lln Power of length dependence forlength offsetLw lw Coefficient of width dependencefor length offsetLwn lwn Power of width dependence forlength offsetLwl lwl Coefficient of length and widthcross term for length offset1.0 none0.0 m Wwn1.0 none0.0 m Wwn+Wln0.0 m Lln1.0 none0.0 m Lwn1.0 none0.0 m Lwn+LlnLlc Llc Coefficient of length dependencefor CV channel lengthoffsetLlm LlnBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-9

Temperature ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteLwc Lwc Coefficient of width dependencefor CV channel lengthoffsetLwlc Lwlc Coefficient of length and widthdependencefor CV channellength offsetWlc Wlc Coefficient of length dependencefor CV channel widthoffsetWwc Wwc Coefficient of widthdependencefor CV channel width offsetWwlc Wwlc Coefficient of length and widthdependencefor CV channelwidth offsetLwLwlWlWwWwlm Lwnm Lwn+Llnm Wlnm Wwnm Wln+WwnA.6 Temperature ParametersSymbolsused inequationSymbolsused inSPICETnom tnom Temperature at which parametersare extractedDescription Default Unit Note27o Cµte ute Mobility temperature exponent-1.5 noneA-10 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Temperature ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteKt1 kt1 Temperature coefficient forthreshold voltageKt1l kt1l Channel length dependence ofthe temperature coefficient forthreshold voltageKt2 kt2 Body-bias coefficient of Vthtemperature effect-0.11 V0.0 Vm0.022 noneUa1 ua1 Temperature coefficient forUa4.31E-9m/VUb1 ub1 Temperature coefficient forUbUc1 uc1 Temperature coefficient forUcAt at Temperature coefficient forsaturation velocityPrt prt Temperature coefficient forRdswAt at Temperature coefficient forsaturation velocitynj nj Emission coefficient of junctionXTI xti Junction current temperatureexponent coefficient-7.61E-18mob-Mod=1,2:-5.6E-11mob-Mod=3:-0.056(m/V) 2m/V 21/V3.3E4 m/sec0.0 Ω-µm3.3E4 m/sec1.0 none3.0 noneBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-11

Flicker Noise Model ParametersSymbolsused inequationSymbolsused inSPICEtpb tpb Temperature coefficient of Pb 0.0 V/Ktpbsw tpbsw Temperature coefficient of 0.0 V/KPbswtpbswg tpbswg Temperature coefficient of 0.0 V/KPbswgtcj tcj Temperature coefficient of Cj 0.0 1/Ktcjsw tcjsw Temperature coefficient ofCjswtcjswg tcjswg Temperature coefficient ofCjswgDescription Default Unit Note0.0 1/K0.0 1/KA.7 Flicker Noise Model ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteNoia noia Noise parameter A (NMOS) 1e20(PMOS) 9.9e18Noib noib Noise parameter B (NMOS) 5e4(PMOS) 2.4e3Noic noic Noise parameter C (NMOS) -1.4e-12(PMOS) 1.4e-12nonenonenoneEm em Saturation field 4.1e7 V/mA-12 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Process ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteAf af Flicker noise exponent 1 noneEf ef Flicker noise frequencyexponent1 noneKf kf Flicker noise coefficient 0 noneA.8 Process ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteTox tox Gate oxide thickness 1.5e-8 mToxm toxm Tox at which parameters areextractedTox m nI-3Xj xj Junction Depth 1.5e-7 mγ1 gamma1 Body-effect coefficient near thesurfacecalculatedV 1/2nI-5γ2 gamma2 Body-effect coefficient in thebulkcalculatedV 1/2nI-6Nch nch Channel doping concentration 1.7e17 1/cm 3 nI-4Nsub nsub Substrate doping concentration 6e16 1/cm 3Vbx vbx Vbs at which the depletionregion width equals xtcalculatedVnI-7Xt xt Doping depth 1.55e-7 mBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-13

Geometry Range ParametersA.9 Geometry Range ParametersSymbolsused inequationSymbolsused inSPICEDescription Default Unit NoteLmin lmin Minimum channel length 0.0 mLmax lmax Maximum channel length 1.0 mWmin wmin Minimum channel width 0.0 mWmax wmax Maximum channel width 1.0 mbinUnit binunit Bin unit scale selector 1.0 noneA.10Model Parameter NotesnI-1. If V th0 is not specified, it is calculated byVth0= VFB+ Φs+ K1Φswhere the model parameter V FB =-1.0. If V th0 is specified, V FB defaults toVVKFB=th0−Φs−1ΦsnI-2. If K 1 and K 2 are not given, they are calculated based onK= γ2− K212Φ−sV bmBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-14

Model Parameter NotesK2( γ1−γ)( Φs−Vbx− Φs)Φs( Φs−Vbm− Φs) + Vbm=22whereΦ sis calculated byΦs=2Vtm0⎛ Nln⎜⎝ nich⎟ ⎞⎠Vtm 0=kBTqnomni= 1.45 × 1010⎛ Tnom⎞⎜ ⎟⎝ 300.15 ⎠1.5⎛Eexp⎜ 21.5565981 −⎝2Vg 0tm0⎞⎟⎠Eg02nom−47.02×10 T= 1.16 −T + 1108nomwhere E g0 is the energy bandgap at temperature T nom .nI-3.If pscbe2

Model Parameter NotesnI-4. If N ch is not given andγ 1is given, N ch is calculated fromNch2γ1C=2qε2oxsiIf both and N ch are not given, N ch defaults to 1.7e23 m -3 and isγ 1γ 1calculated from N ch .nI-5. Ifγ 1is not given, it is calculated byγ1 =2qεNCsioxchnI-6. Ifγ 2is not given, it is calculated byγ2=2qεNCsioxsubnI-7. If V bx is not given, it is calculated byqNchX2εsi2t= Φs−VbxnC-1. If Cgso is not given, it is calculated byif (dlc is given and is greater 0),Cgso = dlc * Cox - Cgs1if (Cgso < 0)Cgso = 0else Cgso = 0.6 Xj * CoxnC-2. If Cgdo is not given, it is calculated byif (dlc is given and is greater than 0),BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-16

Model Parameter NotesCgdo = dlc * Cox - Cgd1if (Cgdo < 0)Cgdo = 0else Cgdo = 0.6 Xj * CoxnC-3. If CF is not given then it is calculated usin byCF = ⎛ + × −2ε⎞⎜1 4 10 7oxln⎟π ⎝ Tox ⎠nC-4.If (acde < 0.4) or (acde > 1.6), a warning message will be given.If (moin < 5.0) or (moin > 25.0), a warning message will be given.If (noff < 0.1) or (noff > 4.0), a warning message will be given.If (voffcv < -0.5) or (voffcv > 0.5), a warning message will be given.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-17

Model Parameter NotesBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley A-18

APPENDIX B: Equation ListB.1 I-V ModelB.1.1 Threshold VoltageVth= V+ K− D− Dth0ox1ox⎛⎜⎜⎝VT 0wVT 0+ K1ox1+⎛ ⎛ − ⎜exp⎜ − D⎝ ⎝NlxLsub⋅eff⎛ ⎛⎜exp⎜ − D⎝ ⎝⎛ ⎛⎜exp⎜ − D⎝ ⎝LVT1eff2lΦVT1wtos⎞−1⎟⎟⎠−VLeff2lWtbseffΦeffs2l' Ltw− K+( K + K V )eff2ox3⎞ ⎛ ⎟ + 2exp⎜ − D⎠ ⎝Vsubbseff3b⎞ ⎛ ⎟ + 2exp⎜ − D⎠ ⎝LlVT 1efftobseff⎞ ⎛ ⎟ + 2exp⎜ − D⎠ ⎝L⎞⎞⎟⎟⎠⎠lToxΦW ' + WeffteffVT1w⎞⎞⎟⎟⎠⎠W( V − Φ )biefftweff( E tao+ E tabV bseff) V ds0l' Lss⎞⎞⎟⎟⎠⎠( V − Φ )bisVth0ox= Vth0− K1⋅ΦsKox= K 1T⋅Toxoxm1oxmK2 ox= K 2T⋅ToxBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-1

I-V Modellt = ε siXdep / Cox ( 1 + DVT 2Vbseff)ltw = ε siXdep / Cox( 1 + DVT 2 wVbseff)lto = εsiXdep0 / CoxXdep=2ε si( Φs − Vbseff)qNchXdep02εsiΦs=qNch(δ1=0.001)Vbseff = Vbc + 05 .[ Vbs −Vbc − δ1+ ( Vbs −Vbc −δ1) 2 −4δ1Vbc]Vbc2⎛ K⎜1= 0.9Φs−2⎝ 4K2⎞⎟⎠VbiNchNDS= vtln( )2niB.1.2 Effective (V gs -V th )Vgsteff⎡ Vgs− Vth⎤2nvtln⎢1+exp( )nvt=⎣ 2⎥⎦2ΦsVgs − Vth − 2Voff1+ 2n COXexp( −)qεsiNch2 nvtB-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

I-V ModelC C V C V D L effDL effdsc + dscd ds +⎛dscb bseff − VT + −⎞( ) ⎜exp( 1 ) 2exp( VT1) ⎟Cd⎝ 2ltlt⎠ Cn= 1+ Nfactor++CoxCoxCitoxCdsi= εXdepB.1.3 MobilityFor mobMod=1µeffµ o=Vgsteff+ 2Vthgsteff thUa UcVbseffU V + 2 V 21 + ( + )( ) + b( )TOXTOXFor mobMod=2µeffµ o=Vgsteffgsteff1 + ( Ua UcVbseffUV + )( ) + b( )TOXTOX2For mobMod=3µeffµ o=gsteff thgsteff thU V + 2 VaU V + 2 V 21 + [ ( ) + b( ) ]( 1 + UV c bseff)TOXTOXBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-3

I-V ModelB.1.4 Drain Saturation VoltageFor R ds > 0 or λ ≠ 1:b b acVdsat = − − 2− 42aa = A W ν C R + ( −1)Aλ1bulk 2 eff sat ox DS bulk⎛2b =− ⎜( V + 2v )( − 1) + A E L + 3A ( V + 2v ) W ν C R⎝λgsteff t bulk sat eff bulk gsteff t eff sat ox DS⎞⎟⎠2c = ( V + 2v) E L + 2( V + 2v)W ν C Rgsteff t sat eff gsteff t eff sat ox DSFor R ds = 0 and λ = 1:λ = AVgsteff+ A1 2Vdsat=Esat Leff ( Vgsteff + 2vt)Abulk Esat Leff + ( Vgsteff + 2vt)Abulk⎛⎜= ⎜1+⎜ 2⎝K1oxΦ −Vsbseff⎛⎜⎜L⎝effA L0+ 2effX XJdep⎛⎜⎜1−A V⎝gs gsteff⎛⎜⎜⎝LeffL+ 2effX XJdep2⎞ ⎞ ⎞⎞⎟ ⎟ B ⎟0⎟ 1+ ⎟⎟⋅⎟ ⎟Weff'+ B1⎟ 1+KetaV⎠ ⎠ ⎠⎠bseffB-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

I-V ModelEsatsat= 2νµ effB.1.5 Effective V ds2( δ ( δ)4δ)1V = V − V −V − + V −V − + V2dseff dsat dsat ds dsat ds dsatB.1.6 Drain Current ExpressionIdsI=R I1 +Vdso( Vdseff )ds dso( Vdseff )dseff⎛ Vds− VdseffVdsV⎜ +⎞ −1 ⎟⎛⎜1+⎝ VA⎠⎝VASCBEdseff⎞⎟⎠Idso=VdseffWeffµ effCoxVgsteff ( 1 − AbulkV2( Vgsteff+ 2vt) )Leff[ 1 + Vdseff /( EsatLeff)]dseffVAPvagVgsteff1 1 −1= VAsat+ ( 1+ )( + )EsatLeff VACLM VADIBLCVACLM=A E L + VPCLMAbulkEsatlitlbulk sat eff gsteff( Vds−Vdseff)BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-5

I-V ModelVADIBLC=θ( Vgsteff+ 2vt)t 1 + P Vrou ( DIBLCB bseff )⎛⎜1−⎝AbulkVdsat⎞⎟AbulkVdsat + Vgsteff + 2vt⎠⎡LL ⎤exp( ) exp( ) P⎣2ll ⎦⎥ +effeffθrout = PDIBLC 1 DROUTDROUT⎢− + 2 −t 0 t 0DIBLC2V⎛ −Plitl⎞exp⎜⎟⎝ Vds−Vdseff⎠1 scbe2 scbe1ASCBEP=LeffVAsat=AbulkVdsatEsatLeff + Vdsat + 2RDSνsatCoxWeff Vgsteff[1−2 ( Vgsteff+ 2 vt) ]2/λ− 1+RDSνsatCoxWeffAbulksiToxXlitl = ε ε oxjB.1.7 Substrate Currentα0+ α1⋅ Leff⎛ β ⎞Isub=1Leff⎝⎠ 1 +V−V⎛( )⎟ ⎞⎜0⎟Ids 0ds dseffVds− Vdseffexp −⎜ +V −dsV RdseffdsIds 0 ⎝ VA ⎠dseffVB-6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

I-V ModelB.1.8 Polysilicon Depletion Effect21qNN gate poly Xpolypoly = XpolyEpoly=2 2εsiε E = ε E = 2qεN gate Vox ox si poly si poly polyV −V− Φ = V + VgsFBspolyox2( −V− Φ −V) −V= 0a VgsFBspolypolya =2εox22qεsiNgateToxVgs_eff( V −V−Φ )2 ⎛2qε⎞siNgateTox= +Φ +⎜ 2εox gs FB sVFBs1+−12 ⎜2εoxqεsiNgateTox⎝⎠B.1.9 Effective Channel Length and WidthLeff= Ldrawn−2dLWeff= Wdrawn−2dWBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-7

I-V Model'Weff= Wdrawn−2dW'dW = dW'+ dW VdW'= WintgW+LlW lngsteffW+W+ dWwWwnb( Φ −V− Φ )sW+L WwlW ln WwnbseffsLlLwdL = L + + +L LwnL W Lwlint ln LlnLwnLWB.1.10Source/Drain ResistanceRds=Rdsw( 1+P V + P ( Φ −V− Φ)rwggsteffrwb6 W( 10 W ') reffsbseffsB.1.11Temperature EffectsVth ( T) = Vth ( Tnorm) + ( KT 1+ Kt 1l / Leff + KT 2Vbseff )( T/ Tnorm−1)Tµ oT ( ) = µ oTnorm ( )( )Tnormµ tevsat ( T) = vsat ( Tnorm ) −AT( T/ Tnorm−1)B-8 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Capacitance Model EquationsTRdsw( T ) = Rdsw( Tnorm) + P r t( −1)TnormUa( T ) = Ua( Tnorm) + Ua1( T / Tnorm−1)Ub( T ) = Ub( Tnorm) + Ub1( T / Tnorm−1)Uc( T ) = Uc( Tnorm) + Uc1( T / Tnorm−1)B.2 Capacitance Model EquationsB.2.1 Dimension DependenceLactive = Ldrawn −2δLeffWactive = Wdrawn −2δWeffδLeffLlc= DLC+LLwcW+ +Lln LwnLwlclnL WLwnδWeffWlc= DWC+LWwcW+ +W ln WwnWwlcW lnL WWwnBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-9

Capacitance Model EquationsB.2.2 Overlap CapacitanceB.2.2.1 Source Overlap Capacitance(1) for capMod = 0Qoverlap,sWactive= CGS0Vgs(2) for capMod = 1If V gs < 0QWCKAPPA ⋅ CGS1⎛+⎜ − 1 +2 ⎜⎝Vgs1 −CKAPPAoverlap , s4= CGS 0 ⋅Vgsactive⎞⎟⎟⎠ElseQoverlap,sWactive( CGS0+ CKAPPA⋅CGS ) ⋅Vgs= 1(3) for capMod = 2QW⎛+ CGS1⎜V⎜⎝CKAPPA⎛− ⎜−1+2 ⎜⎝V ⎞⎞gs overlap1−⎟⎟CKAPPA⎟⎟⎠⎠overlap , s= CGS0⋅Vgsgs−Vgs, overlap4,activeV2( V + δ ) 4δ⎟⎞, 0. 02 ⎠1= ⎜ ⎛ V + δ1−1 1 12⎝+gsgsδgs, overlap=B-10 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Capacitance Model EquationsB.2.2.2 Drain Overlap Capacitance(1) for capMod = 0Qoverlap,dWactive= CGD0Vgd(2) for capMod = 1If V gd < 0ElseQWCKAPPA⋅CGD1⎛+⎜−1+2 ⎜⎝V ⎞gd1−⎟CKAPPA⎟⎠overlap,d4= CGD0⋅VgsactiveQoverlap , dWactive( CGD0+ CKAPPA ⋅ CGD ) ⋅Vgd= 1(3) for capMod = 2QW⎛+ CGD1⎜V⎜⎝CKAPPA⎛− ⎜−1+2 ⎜⎝V ⎞⎞gd overlap1−⎟CKAPPA⎟⎠⎠overlap , d4,= CGD0⋅Vgdgd−Vgd,overlapactiveV2( V + δ ) 4δ⎞⎟, 0. 021= ⎜ ⎛ V +1−1 1 12 ⎝+gdδgdδ⎠gd, overlap=BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-11

Capacitance Model EquationsB.2.2.3 Gate Overlap Charge( )Q =− Q + Qoverlap,g overlap,s overlap,dB.2.3 Instrinsic Charges(1) capMod = 0a. Accumulation region (V gs < V fbcv + V bs )Qg= WactiveLactiveCox( V −V−V)gsbsfbcvQ= −subQ gQ inv= 0b. Subthreshold region (V gs < V th )Qsub0( V −V−V)2K ⎛ 41ox= − ⋅ ⎜gsWactiveLactiveCox−1+1+⎜22⎝K1oxfbcvbs⎞⎟⎟⎠Qg=−QbB-12 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Capacitance Model EquationsQ inv= 0c. Strong inversion (V gs > V th )Vgs−VthVdsat,cv=Abulk'CLE⎛⎞⎜ ⎛ CLC ⎞A ⎟bulk' = Abulk01+⎜⎜⎟⎟⎝ ⎝ Leff ⎠ ⎠⎛K ⎛ A Loxeff BA⎜1 ⎜ 00bulk0=⎜1++2 ΦWs−V⎜bseffLeffXJXdep eff+ B⎝⎝+ 2'Vth= Vfbcv+ Φs+ K1oxΦs−Vbseff(i) 50/50 Charge partitionIf V ds < V dsat1⎞⎞⎟⎟1⋅⎟⎟1+KetaV⎠⎠bseffQ = C WgoxLactive active⎛⎜⎜V⎜⎜⎝gs−VfbcvVds−Φs−2+⎛12⎜V⎝gsAbulk−Vth2' VdsAbulk'V−2ds⎞⎟⎟⎞⎟⎟⎟⎠⎠BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-13

Capacitance Model Equations2 2Abulk ' Vds Abulk ' VdsQinv =−Wactive LactiveCox[Vgs −Vth− +2A12(Vgs−Vth−2bulk'Vds])( 1−Abulk ') Vds ( 1 − Abulk ') Abulk ' VdsQb = Wactive LactiveCox[Vfb − Vth + Φs+−2Abulk'12(Vgs−Vth− V22ds])A V A VQs Qd inv Wactive LactiveC ox V gs V th bulk ' ds bulk ' ds= = 05Q . =− [ − − +2A12(Vgs−Vth−2otherwise2 2bulk]'Vds)VdsatQg = Wactive LactiveCox( Vgs −Vfb −Φs− )31Qs = Qd = − Wactive LactiveCox( Vgs −Vth)3( 1 − Abulk') VQb =− Wactive LactiveCox(Vfb + Φs − Vth+3dsat)(ii) 40/60 channel-charge PartitionB-14 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Capacitance Model Equationsif (V ds < V dsat )Vds Abulk VdsQg = CoxWactive Lactive [ Vgs −Vfb −Φs− +]'2AbulkVds12( Vgs−Vth− )2'22 2Abulk ' Vds Abulk ' VdsQinv =−Wactive LactiveCox[Vgs −Vth− +2A12(Vgs−Vth−2bulk'Vds])( 1−Abulk ') Vds ( 1−Abulk ') Abulk ' VdsQb = Wactive LactiveCox[Vfb − Vth + Φs+−2Abulk'12(Vgs−Vth− V22ds])Q =−W L Cd active active ox⎡⎢AVgs − Vth Abulk'⎢ − Vds+⎢ 2 2⎣⎢bulk2 2Vgs − Vth Abulk Vds Vgs − Vth Abulk Vds' Vds[ ( ) −' ( ) +( ' )6 8 40Abulk'2( Vgs−Vth− Vds)2⎤⎥⎥⎥⎦⎥Qs =− ( Qg+ Qb+Qd)otherwiseVdsatQg = Wactive LactiveCox( Vgs −Vfb −Φs− )3BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-15

Capacitance Model Equations4Qd =− Wactive LactiveCox( Vgs −Vth)15Qs =− ( Qg+ Qb+Qd)( 1−Abulk') VQb =− Wactive LactiveCox(Vfb + Φs − Vth+3(iii) 0/100 Channel-charge Partitionif V ds < V dsatdsat)Vds Abulk VdsQg = CoxWactive Lactive [ Vgs −Vfb −Φs− +]'2AbulkVds12( Vgs−Vth− )2'22 2Abulk ' Vds Abulk ' VdsQinv =−Wactive LactiveCox[Vgs −Vth− +2A12(Vgs−Vth−2bulk'Vds])( 1−Abulk ') Vds ( 1−Abulk ') Abulk ' VdsQb = Wactive LactiveCox[Vfb − Vth + Φs+−2Abulk'12(Vgs−Vth− V22ds])B-16 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

Capacitance Model Equations⎡Q W L C V V A 2⎢ gs − th bulk ' ( Abulk' Vds)d=−active active ox⎢+ Vds−A⎢ 2 424(Vgs−Vth−⎣2bulk'Vds⎤⎥⎥) ⎥⎦Qs =− ( Qg+ Qb+Qd)otherwiseVdsatQg = Wactive LactiveCox( Vgs −Vfb −Φs− )3( 1 − Abulk') VQb =− Wactive LactiveCox(Vfb + Φs − Vth+3dsat)Q d= 0( ) Q gQ bQs = − +(2) capMod = 1The flat-band voltage V fb is calculated fromVfb= Vth− Φs− K1oxΦs−VbseffBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-17

Capacitance Model Equationswhere the bias dependences of V th given in Section B.1.1 are notconsidered in calculating V fb for capMod = 1.if (V gs < V fb + V bs + V gsteffcv )( )Q 1 =−W L C V −Vfb −V −Vg active active ox gs bs gsteffcvelseQg1( V −V−V−V)2K ⎛⎜ 41oxgs fb= WactiveLactiveCox⋅ −1+1+⎜22 K⎝1oxgsteff , CVbseff⎞⎟⎟⎠Q=−Qb1 g1Vdsat,cv=VgsteffcvAbulk'Abulk⎛'= Abulk+ ⎛ ⎝ ⎜ ⎞01⎜⎟⎝ Leff⎠CLC CLE⎞⎟⎠Abulk0⎛=⎜+⎜12⎝Ks1oxΦ −Vbseff⎛⎜⎜⎝LeffA L0+ 2effXJXdepB ⎞⎞0 ⎟⎟1+ ⋅Weff' + B ⎟⎟11+KetaV⎠⎠bseffBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-18

Capacitance Model EquationsVgsteff , cv= noff⋅ nvt⎛ ⎛Vln⎜1+exp⎜⎝ ⎝gs−Vth− voffcv ⎞⎞⎟⎟noff ⋅ nvt ⎠⎠if (V ds

Capacitance Model EquationsQsWactive LactiveCox=−⎛ AVgsteff cv bulk '2⎜− V⎝ 2ds⎞⎟⎠2⎛ 422⎜V − V A V + V A V − A V⎝ 3315( ' ) ( ' ) ( ' )3 2 2 3gsteffcv gstefcvf bulk ds gsteffcv bulk ds bulk ds⎞⎟⎠Q =− ( Q + Q + Q )d g b s(iii) 0/100 Channel-charge Partition⎛⎜( )Q W L C V gstefcv Abulk Vds Abulk Vdss=− ⎜''active active ox+ −2 4 ⎛ A⎜24⎜Vgsteffcv−⎝⎝ 22bulk'Vds⎞⎟⎟⎞⎟⎠⎟⎠Q =− ( Q + Q + Q )d g b sif (V ds > V dsat )VQ = Q + W L C⎛1⎜V−⎝ 3g g active active ox gsteff cv dsat⎞⎟⎠( gsteffcv − dsat )Q Q W L C V Vb = b1 − active active ox3BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-20

Capacitance Model Equations(i) 50/50 Channel-charge PartitionQs= Wactive LactiveCoxQd= − V3gsteff cv(ii) 40/60 Channel-charge PartitionQsWactive LactiveCox=− 2 V5gsteffcvQ =− ( Q + Q + Q )d g b s(iii) 0/100 Channel-charge PartitionQ =−W L Cs active active ox2Vgstefcv3Q =− ( Q + Q + Q )d g b s(3) capMod = 2The flat-band voltage V fb is calculated fromvfb= Vth− Φs− K1oxΦ −VsbseffBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-21

Capacitance Model Equationswhere the bias dependences of V th given in Section B.1.1 are notconsidered in calculating V fb for capMod = 2.( )Q =− Q + Q + Q + Qg inv acc sub0 δsubQ = Q + Q + Qb acc sub0 δsubQinv = Qs + Qd2{ 3 3 }V = vfb− 05 . V + V + 4δ vfb where V = vfb−V− δ ; δ = 002 .FBeff3 3 gb 3 3( )Q =−W L C V −vfbacc active active ox FBeffQsub0( V −V−V−V)2K ⎛⎜ 41oxgs FBeff= −WactiveLactiveCox⋅ − 1 + 1 +⎜22⎝K1oxgsteff , CVbseff⎞⎟⎟⎠Vdsat,cvVgstefcvf= gsteff,cvAbulk'Abulk⎛' = Abulk+ ⎛ ⎝ ⎜ ⎞0 ⎜1 CLC CLE⎟⎝ Lactive⎠BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-22

Capacitance Model EquationsAbulk0⎛=⎜1+⎜ 2⎝Ks1oxΦ −Vbseff⎛⎜⎜⎝LeffA L0+ 2effXJXdepB ⎞⎞0 ⎟⎟1+ ⋅Weff' + B ⎟⎟11+KetaV⎠⎠bseffVgsteff , cv= noff ⋅ nvt⎛ ⎛Vln⎜1+exp⎜⎝ ⎝gs−Vth− voffcv⎞⎞⎟⎟noff ⋅ nvt ⎠⎠2{ 4 4dsat,cv}V = V − 05 . V + V + 4δ V where V = V −V− δ ; δ = 002 .cveffdsat , cv4 4 dsat,cv ds 4 4⎛⎜⎛ AQ =−W L C ⎜⎜V−⎝ 2⎜⎝inv active active ox gsteff cv bulk'Vcveff⎞ A⎟ +⎠ ⎛12⎜V⎝bulkgsteff cv'V2 2cveffA−2bulk'Vcveff⎞⎟⎟⎞⎟⎠⎟⎠δQ = W L Csub active active ox⎛⎜⎜1 − A2⎜⎝bulk( 1 − )' A ' A ' VVcveff−⎛ Abulk'12⎜Vgsteffcv− V⎝ 22bulk bulk cveffcveff⎞⎟⎟⎞⎟⎠⎟⎠BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-23

Capacitance Model EquationsB.2.3.1 50/50 Charge partition⎛⎜W L C AAactive active oxQs Qd QinvVgsteff cv bulk= = =− ⎜ '05 .− Vcveff+2 ⎜ 2 ⎛⎜12⎜V⎝⎝V2 2bulk cveffgsteffcv'A−2bulkVcveff⎞⎟⎟⎞⎟⎟⎟⎠⎠B.2.3.2 40/60 Channel-charge PartitionQ22( ' ) ( ' ) ( ' )WactiveLactiveCoxQs=−⎛ 3 4 2⎜V − V A V + V A V −2A V⎛ AVgsteff cv bulk ⎞ ⎝gsteffc'33152⎜− Vcveff ⎟⎝ 2 ⎠d2 3gsteffcv gstefcvf bulk cveff gsteff bulk cveff bulk cveff1( ' ) ( ' ) ( ' )WactiveLactiveCox=−⎛ 3 5 2V − V A V + V A V −2⎜A V⎛ Abulk⎞ ⎝gsteffc'352⎜Vgsteffcv− Vcveff ⎟⎝ 2 ⎠gsteffcv gsteff cv bulk cveff gsteff cv bulk cveff bulk cveff⎞⎟⎠2 3⎞⎟⎠B.2.3.3 0/100 Charge Partition⎛⎜Q W L C V gsteffcv A V A Vgstefcvf bulk'cveff bulk cveffs=− ⎜active active ox+ −2 4 ⎛ A⎜24⎜Vgsteffcv−⎝⎝ 2( ' )bulk2'V⎛( )Q W L C V A V A V2⎜gsteffcv3bulk'cveff bulk'cveffd=− ⎜active active ox− +2 4 ⎛ Abulk'⎜8⎜Vgsteffcv− V⎝⎝ 2cveffcveff⎞⎟⎟⎞⎟⎠⎟⎠⎞⎟⎟⎞⎟⎠⎟⎠BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-24

Capacitance Model Equations(3) capMod = 3 (Charge-Thickness Model)capMod = 3 also uses the bias-independent V th to calculate V fb as incapMod = 1 and 2.vfb= Vth− Φs− K1oxΦ −VsbseffFor the finite charge thickness (X DC ) formulations, refer to Chapter 4.Qacc= WLCoxeff⋅Vgbacc1= ⋅22[ V0 + V0+ 4δ]Vgbacc 3V fbV0= Vfb+ Vbseff−Vgs− δ 32{ 3 3 }V = vfb− 05 . V + V + 4δ vfb where V = vfb−V− δ ; δ = 002 .FBeff3 3 gb 3 3CoxeffC=CoxoxCcen+ Ccenε=CsicenXDCBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-25

Capacitance Model EquationsΦ⎛⎜V= νtln⎜⎝⋅ ( V+ 2KgsteffCV gsteffCVδ= Φs− 2ΦB2moin ⋅ K1oxν1ox2tΦB⎞⎟⎟⎠Qsub0= −WLCoxeff2oxK1⋅2⎡⋅ ⎢-1+⎢⎣4 V1+( −V−V−V)gsFBeffK21oxbseffsgsteff,cv⎤⎥⎥⎦=1− ⋅22( V1 + V1+ 4δVdsat)VcveffVdsat3V1= V dsat−Vds−δ 3VdsatV=gsteff , cvAbulk− ϕ δ'Qinv= −WLCoxeff⎡⎢⋅ ⎢V⎢⎢⎣gsteff,cv1−ϕδ− A2bulk' Vcveff+⎛12⋅⎜V⎝Agsteff,cv'2bulk−ϕδV2cveffA−bulk' Vcveff⎤⎥⎥⎞⎥2⎟⎥⎠ ⎦BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-26

Capacitance Model EquationsδQsub= WLCoxeff⎡⎢1− A⋅ ⎢⎢ 2⎢⎣bulk'Vcveff−⎛12 ⋅ ⎜V⎝( 1 − A ')gsteff , cvbulk−ϕ δ⋅ AbulkA−' Vbulk2cveff' Vcveff2⎤⎥⎥⎞⎥⎟⎥⎠ ⎦(i) 50/50 Charge PartitionQ = QSD1= Q2invWLC=−2oxeff⎡⎢⎢V⎢⎢⎣gsteffcv ,(ii) 40/60 Charge Partition1−ϕδ− A2bulk' Vcveff+⎛12⋅⎜V⎝Agsteffcv ,'2bulkV2cveffA−ϕ−δbulk' Vcveff⎤⎥⎥⎞⎥2⎟⎥⎠ ⎦QS=−⎛2⎜V⎝gsteffcv ,WLCoxeffA−ϕ−δbulk' Vcveff⎡2 ⎢⎞ ⎣2⎟⎠3 42 22 23⎤( V −ϕ) − ( V −ϕ) A ' V + ( V −ϕ)( A ' V ) − ( A ' V ) ⎥⎦gsteff , cvδ3gsteff , cvδbulkcveff3gsteff , cvδbulkcveff15bulkcveffQD=−⎛2⎜V⎝gsteff , cvWLCoxeffA−ϕ−δbulk' Vcveff⎡2 ⎢⎞ ⎣2⎟⎠(iii) 0/100 Charge Partition3 522 13⎤( V −ϕ) − ( V −ϕ) A ' V + ( V −ϕ)( A ' V ) − ( A ' V ) ⎥⎦gsteff , cvδ3gsteff , cvδbulkcveffgsteff , cvδbulkcveff5bulkcveffQSWLC=−2oxeff⎡⎢⋅ ⎢V⎢⎢⎣gsteff,cv1−ϕδ+ A2bulk' Vcveff−⎛12⋅⎜V⎝Agsteff,cv'2bulk−ϕδV2cveffA−bulk' Vcveff⎤⎥⎥⎞⎥2⎟⎥⎠⎦BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-27

Capacitance Model EquationsQDWLC= −2oxeff⎡⎢⋅ ⎢V⎢⎢⎣gsteff,cv3−ϕδ−2Abulk' Vcveff+⎛4⋅⎜V⎝gsteff,cvA'2bulk−ϕδV2cveffA−bulk' Vdveff⎤⎥⎥⎞⎥2⎟⎥⎠⎦BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley B-28

APPENDIX C: References[1] G.S. Gildenblat, VLSI Electronics: Microstructure Science, p.11, vol. 18, 1989.[2] Muller and Kamins, Devices Electronics for Integrated Circuits, Second Edition.[3] J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, M. Chan, P. K. Ko and C. Hu., BSIM3Version 2.0 User’s Manual, March 1994.[4] J.A. Greenfield and R.W. Dutton, "Nonplanar VLSI Device Analysis Using theSolution of Poisson's Equation," IEEE Trans. Electron Devices, vol. ED-27, p.1520,1980.[5] H.S. Lee. "An Analysis of the Threshold Voltage for Short-Channel IGFET's," Solid-State Electronics, vol.16, p.1407, 1973.[6] G.W. Taylor, "Subthreshold Conduction in MOSFET's," IEEE Trans. ElectronDevices, vol. ED-25, p.337, 1978.[7] T. Toyabe and S. Asai, "Analytical Models of Threshold Voltage and BreakdownVoltage of Short-Channel MOSFET's Derived from Two-Dimensional Analysis,"IEEE J. Solid-State Circuits, vol. SC-14, p.375, 1979.[8] D.R. Poole and D.L. Kwong, "Two-Dimensional Analysis Modeling of ThresholdVoltage of Short-Channel MOSFET's," IEEE Electron Device Letter, vol. ED-5,p.443, 1984.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley C-1

[9] J.D. Kendall and A.R. Boothroyd, "A Two-Dimensional Analytical Threshold VoltageModel for MOSFET's with Arbitrarily Doped Substrate," IEEE Electron DeviceLetter, vol. EDL-7, p.407, 1986.[10] Z.H. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, and Y.C. Cheng,"Threshold Voltage Model For Deep-Submicrometer MOSFETs," IEEE Tran.Electron Devices, vol. 40, pp. 86-95, Jan., 1993.[11] Y.C. Cheng and E.A. Sullivan, "Effect of Coulombic Scattering on Silicon SurfaceMobility," J. Appl. Phys. 45, 187 (1974).[12] Y.C. Cheng and E.A. Sullivan, Surf. Sci. 34, 717 (1973).[13] A.G. Sabnis and J.T. Clemens, "Characterization of Electron Velocity in the Inverted Si Surface," Tech. Dig.- Int. Electron Devices Meet., pp. 18-21 (1979).[14] G.S. Gildenblat, VLSI Electronics: Microstructure Science, p. 11, vol. 18, 1989.[15] M.S. Liang, J.Y. Choi, P.K. Ko, and C. Hu, "Inversion-Layer Capacitance andMobility of Very Thin Gate-Oxide MOSFET's," IEEE Trans. Electron Devices, ED-33, 409, 1986.[16] F. Fang and X. Fowler, "Hot-electron Effects and Saturation velocity in SiliconInversion Layer," J. Appl. Phys., 41, 1825, 1969.[17] E. A. Talkhan, I. R. Manour and A. I. Barboor, "Investigation of the Effect of Drift-Field-Dependent Mobility on MOSFET Characteristics," Parts I and II. IEEE Trans.on Electron Devices, ED-19(8), 899-916, 1972.C-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

[18] M.C. Jeng, "Design and Modeling of Deep-Submicrometer MOSFETs," Ph. D.Dissertation, University of California.[19] K.Y. Toh, P.K. Ko and R.G. Meyer, "An Engineering Model for Short-channel MOSDevices," IEEE Jour. of Solid-State Circuits, vol. 23, No. 4, Aug. 1988.[20] C. Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan and K.W. Kyle, "Hot-Electron InducedMOSFET Degradation - Model, Monitor, Improvement," IEEE Tran. on ElectronDevices, Vol. 32, pp. 375-385, Feb. 1985.[21] F.C. Hsu, P.K. Ko, S. Tam, C. Hu and R.S. Muller, "An Analytical BreakdownModel for Short-Channel MOSFET's," IEEE Trans. on Electron Devices, Vol.ED-29, pp. 1735, Nov. 1982[22] H. J. Parke, P. K. Ko, and C. Hu, “ A Measurement-based Charge Sheet CapacitanceModel of Short-Channel MOSFET’s for SPICE,” in IEEE IEDM 86, Tech. Dig., pp.485-488, Dec. 1986.[23] M. Shur, T.A. Fjeldly, T. Ytterdal, and K. Lee, “ A Unified MOSFET Model,” Solid-State Electron., 35, pp. 1795-1802, 1992.[24] MOS9 Documentation.[25] C. F. Machala, P. C. Pattnaik and P. Yang, "An Efficient Algorithms for theExtraction of Parameters with High Confidence from Nonlinear Models," IEEEElectron Device Letters, Vol. EDL-7, no. 4, pp. 214-218, 1986.[26] Y. Tsividis and K. Suyama, “MOSFET Modeling for Analog Circuit CAD: Problemsand Prospects,” Tech. Dig. vol. CICC-93, pp. 14.1.1-14.1.6, 1993.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley C-3

[27] C. L. Huang and G. Sh. Gildenblat, "Measurements and Modeling of the n-channelMOSFET Inversion Layer Mobility and Device Characteristics in the TemperatureRange 60-300 K," IEEE Tran. on Electron Devices, vol. ED-37, no.5, pp. 1289-1300, 1990.[28] D. S. Jeon, et al, IEEE Tran. on Electron Devices, vol. ED-36, no. 8, pp1456-1463,1989.[29] S. M. Sze, Physics of Semiconductor Devices, 2nd Edition.[30] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, SecondEdition.[31] R. Rios, N. D. Arora, C.-L. Huang, N. Khalil, J. Faricelli, and L. Gruber, “A physicalcompact MOSFET model, including quantum mechanical effects, for statisticalcircuit design applications”, IEDM Tech. Dig., pp. 937-940, 1995.[32] Weidong Liu, Xiaodong Jin, Ya-Chin King, and Chenming Hu, “An efficient andaccurate compact model for thin-oxide-MOSFET intrinsic capacitance consideringthe finite charge layer thickness”, IEEE Trans. on Electron Devices, vol. ED-46,May, 1999.[33] Mansun Chan, et al, "A Relaxation time Approach to Model the Non-Quasi-StaticTransient Effects in MOSFETs," IEDM, 1994 Technical Digest, pp. 169-172, Dec.1994.[34] P. K. Ko, “Hot-electron Effects in MOSFET’s”, Ph. D Dissertation, University ofCalifornia, Berkeley, 1982C-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

[35] K.K. Hung et al, “A Physics-Based MOSFET Noise Model for Circuit Simulators,”IEEE Transactions on Electron Devices, vol. 37, no. 5, May 1990.[36] K.K. Hung et al, “A Unified Model for the Flicker Noise in Metal-OxideSemiconductor Field-Effect Transistors,” IEEE Transactions on Electron Devices,vol. 37, no. 3, March 1990.[37] T.P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill,New York, 1987.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley C-5

C-6 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

APPENDIX D: Model Parameter BinningBelow is the information on parameter binning regarding which model parameters can orcannot be binned. All those parameters which can be binned follow this implementation:PPLP +L= 0effP+WWeff+LeffP× WeffFor example, for the parameter k1: P 0 = k1, P L = lk1, P W = wk1, P P = pk1. binUnit is abining unit selector. If binUnit = 1, the units of L eff and W eff used in the binning equationabove have the units of microns; therwise in meters.For example, for a device with L eff = 0.5µm and W eff = 10µm. If binUnit = 1, the parametervalues for vsat are 1e5, 1e4, 2e4, and 3e4 for vsat, lvsat, wvsat, and pvsat, respectively.Therefore, the effective value of vsat for this device isvsat = 1e5 + 1e4/0.5 + 2e4/10 + 3e4/(0.5*10) = 1.28e5To get the same effective value of vsat for binUnit = 0, the values of vsat, lvsat, wvsat, andpvsat would be 1e5, 1e-2, 2e-2, 3e-8, respectively. Thus,vsat = 1e5 + 1e-2/0.5e6 + 2e-2/10e-6 + 3e-8/(0.5e-6 * 10e-6) = 1.28e5BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-1

Model Control ParametersD.1 Model Control ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?None level The model selector NONone version Model version selector NONone binUnit Bining unit selector NONone param- Parameter value check NOChkmobMod mobMod Mobility model selector NOcapMod capMod Flag for the short channel NOcapacitance modelnqsMod nqsMod Flag for NQS model NOnoiMod noiMod Flag for Noise model NOD.2 DC ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?Vth0 vth0 Threshold voltage @V bs =0 for YESLarge L.VFB vfb Flat band voltage YESK1 k1 First order body effect coefficientYESK2 k2 Second order body effect coefficientYESD-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley

DC ParametersSymbolsused inequationSymbolsused inSPICEDescriptionK3 k3 Narrow width coefficient YESK3b k3b Body effect coefficient of k3 YESW0 w0 Narrow width parameter YESNlx nlx Lateral non-uniform doping YESparameterDvt0 dvt0 first coefficient of short-channeleffect on VthYESDvt1 dvt1 Second coefficient of shortchanneleffect on VthDvt2 dvt2 Body-bias coefficient of shortchanneleffect on VthDvt0w dvt0w First coefficient of narrowwidth effect on Vth for smallchannel lengthDvt1w dvtw1 Second coefficient of narrowwidth effect on Vth for smallchannel lengthDvt2w dvt2w Body-bias coefficient of narrowwidth effect for small channellengthµ0 u0 Mobility at Temp = TnomNMOSFETPMOSFETUa ua First-order mobility degradationcoefficientUb ub Second-order mobility degradationcoefficientCan BeBinned?YESYESYESYESYESYESYESYESBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-3

DC ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?Uc uc Body-effect of mobility degradationcoefficientνsat vsat Saturation velocity at Temp =TnomA0 a0 Bulk charge effect coefficientfor channel lengthYESYESYESAgs ags gate bias coefficient of Abulk YESB0 b0 Bulk charge effect coefficientfor channel widthYESB1 b1 Bulk charge effect width offset YESKeta keta Body-bias coefficient of bulk YEScharge effectA1 a1 First non0saturation effect YESparameterA2 a2 Second non-saturation factor YESRdsw rdsw Parasitic resistance per unitwidthYESPrwb prwb Body effect coefficient of Rdsw YESPrwg prwg Gate bias effect coefficient ofRdswWr wr Width Offset from Weff for RdscalculationWint wint Width offset fitting parameterfrom I-V without biasLint lint Length offset fitting parameterfrom I-V without biasYESYESNONOBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-4

DC ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?dWg dwg Coefficient of Weff’s gatedependencedWb dwb Coefficient of Weff’s substratebody bias dependenceVoff voff Offset voltage in the subthresholdregion for large W and LYESYESYESNfactor nfactor Subthreshold swing factor YESEta0 eta0 DIBL coefficient in subthresholdregionYESEtab etab Body-bias coefficient for the YESsubthreshold DIBL effectDsub dsub DIBL coefficient exponent in YESsubthreshold regionCit cit Interface trap capacitance YESCdsc cdsc Drain/Source to channel couplingcapacitanceYESCdscb cdscb Body-bias sensitivity of Cdsc YESCdscd cdscd Drain-bias sensitivity of Cdsc YESPclm pclm Channel length modulationparameterPdiblc1 pdiblc1 First output resistance DIBLeffect correction parameterPdiblc2 pdiblc2 Second output resistance DIBLeffect correction parameterPdiblcb pdiblcb Body effect coefficient ofDIBL correction parametersYESYESYESYESBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-5

DC ParametersSymbolsused inequationSymbolsused inSPICEDescriptionDrout drout L dependence coefficient of theDIBL correction parameter inRoutPscbe1 pscbe1 First substrate current bodyeffectparameterPscbe2 pscbe2 Second substrate current bodyeffectparameterPvag pvag Gate dependence of Early voltageYESYESYESYESδ delta Effective Vds parameter YESNgate ngate poly gate doping concentration YESα0 alpha0 The first parameter of impactionization currentα1 alpha1 Isub parameter for length scalingβ0 beta0 The second parameter of impactionization currentRsh rsh Source drain sheet resistance inohm per squareJs0 js Source drain junction saturationcurrent per unit areaCan BeBinned?YESYESYESNONOijth ijth Diode limiting current NOBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-6

AC and Capacitance ParametersD.3 AC and Capacitance ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?Xpart xpart Charge partitioning rate flag NOCGS0 cgso Non LDD region source-gateoverlap capacitance perchannel lengthNOCGD0 cgdo Non LDD region drain-gateoverlap capacitance perchannel lengthNOCGB0 cgbo Gate bulk overlap capacitanceNOper unit channel lengthCj cj Bottom junction per unit area NOMj mj Bottom junction capacitancegrating coefficientMjsw mjsw Source/Drain side junctioncapacitance grading coefficientNONOCjsw cjsw Source/Drain side junction NOcapacitance per unit areaPb pb Bottom built-in potential NOPbsw pbsw Source/Drain side junction NObuilt-in potentialCGS1 cgs1 Light doped source-gate YESregion overlap capacitanceCGD1 cgd1 Light doped drain-gate regionoverlap capacitanceYESBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-7

AC and Capacitance ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCKAPPA ckappa Coefficient for lightly dopedregion overlapcapacitance Fringing fieldcapacitanceYESCf cf fringing field capacitance YESCLC clc Constant term for the short YESchannel modelCLE cle Exponential term for the short YESchannel modelDLC dlc Length offset fitting parameterYESfrom C-VDWC dwc Width offset fitting parameter YESfrom C-VVfbcv vfbcv Flat-band voltage parameter YES(for capMod = 0 only)noff noff CV parameter in Vgsteff,CV YESfor weak to strong inversionvoffcv voffcv CV parameter in Vgsteff,CV YESfor weak to strong inversionacde acde Exponential coefficient forcharge thickness in capMod=3for accumulation and depletionregionsYESmoin moin Coefficient for the gate-biasdependent surface potentialCan BeBinned?YESBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-8

NQS ParametersD.4 NQS ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?Elm elm Elmore constant of the channel YESD.5 dW and dL ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?Wl wl Coefficient of length dependencefor width offsetWln wln Power of length dependence ofwidth offsetWw ww Coefficient of width dependencefor width offsetWwn wwn Power of width dependence ofwidth offsetWwl wwl Coefficient of length and widthcross term for width offsetLl ll Coefficient of length dependencefor length offsetLln lln Power of length dependence forlength offsetNONONONONONONOBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-9

dW and dL ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?Lw lw Coefficient of width dependencefor length offsetLwn lwn Power of width dependence forlength offsetLwl lwl Coefficient of length and widthcross term for length offsetLlc Llc Coefficient of length dependencefor CV channel lengthoffsetLwc Lwc Coefficient of width dependencefor CV channel lengthoffsetLwlc Lwlc Coefficient of length and widthdependencefor CV channellength offsetWlc Wlc Coefficient of length dependencefor CV channel widthoffsetWwc Wwc Coefficient of widthdependencefor CV channel width offsetWwlc Wwlc Coefficient of length and widthdependencefor CV channelwidth offsetNONONONONONONONONOBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-10

Temperature ParametersD.6 Temperature ParametersSymbolsused inequationSymbolsused inSPICEDescriptionTnom tnom Temperature at which parametersare extractedµte ute Mobility temperature exponentKt1 kt1 Temperature coefficient forthreshold voltageKt1l kt1l Channel length dependence ofthe temperature coefficient forthreshold voltageKt2 kt2 Body-bias coefficient of Vthtemperature effectUa1 ua1 Temperature coefficient forUaCan BeBinned?NOYESYESYESYESYESUb1 ub1 Temperature coefficient for YESUbUc1 uc1 Temperature coefficient for YESUcAt at Temperature coefficient for YESsaturation velocityPrt prt Temperature coefficient for YESRdswnj nj Emission coefficient YESXTI xti Junction current temperatureexponent coefficientYESBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-11

Flicker Noise Model ParametersSymbolsused inequationSymbolsused inSPICEDescriptiontpb tpb Temperature coefficient of Pb NOtpbsw tpbsw Temperature coefficient of NOPbswtpbswg tpbswg Temperature coefficient of NOPbswgtcj tcj Temperature coefficient of Cj NOtcjsw tcjsw Temperature coefficient ofCjswtcjswg tcjswg Temperature coefficient ofCjswgCan BeBinned?NONOD.7 Flicker Noise Model ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?Noia noia Noise parameter A NONoib noib Noise parameter B NONoic noic Noise parameter C NOEm em Saturation field NOAf af Flicker noise exponent NOBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-12

Process ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?Ef ef Flicker noise frequency NOexponentKf kf Flicker noise parameter NOD.8 Process ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?Tox tox Gate oxide thickness NOToxm toxm Tox at which parameters are NOextractedXj xj Junction Depth YESγ1 gamma1 Body-effect coefficient nearthe surfaceYESγ2 gamma2 Body-effect coefficient in the YESbulkNch nch Channel doping concentration YESNsub nsub Substrate doping concentration YESVbx vbx Vbs at which the depletionregion width equals xtVbm vbm Maximum applied body bias inVth calculationYESYESXt xt Doping depth YESBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-13

Geometry Range ParametersD.9 Geometry Range ParametersSymbolsused inequationSymbolsused inSPICEDescriptionCan BeBinned?Lmin lmin Minimum channel length NOLmax lmax Maximum channel length NOWmin wmin Minimum channel width NOWmax wmax Maximum channel width NObinUnit binUnit Binning unit selector NOBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley D-14