EB60 - MachXO2 Control Development Kit User's Guide

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MachXO2 Control Development Kit
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User’s Guide
April 2011
Revision: EB60_01.0

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Introduction
Thank you for choosing the Lattice Semiconductor MachXO2 Control Development Kit!
This guide describes how to start using the MachXO2 Control Development Kit, an easy-to-use platform for rapidly
prototyping system control designs using MachXO2 PLDs. Along with the evaluation board and accessories, this kit
includes a pre-loaded control system-on-chip (Control SoC) design that demonstrates board diagnostic functions
including I/O control, voltage monitoring, time-stamps and data logging to non-volatile memory. The Power Manager
II ispPAC ® -POWR1014A and 8-bit LatticeMico8 microcontroller are featured in the board and demonstration
design.
The contents of this user’s guide include demo operation, top-level functional descriptions of the various portions of
the evaluation board, descriptions of the on-board connectors, switches, a complete set of schematics and bill of
materials for the MachXO2 Control Evaluation Board.
Note: Static electricity can severely shorten the lifespan of electronic components. See the MachXO2 Control
Development Kit QuickSTART Guide for handling and storage tips.
Features
The MachXO2 Control Development Kit includes:
MachXO2 Control Evaluation Board – The MachXO2 Control Evaluation Board features the following on-board
components and circuits:
– MachXO2 LCMXO2-1200HC-csBGA132 PLD. The board is designed for density migration, allowing a
higher-density MachXO2 device (up to 4000 LUTs) to be assembled on the board.
– Power Manager II POWR1014A mixed-signal PLD
– 4 Mbit SPI Flash memory
– microSD (micro Secure Digital) memory socket
– 60-ball VFBGA footprint for LPDDR memory. When populated, 128-Mbit LPDDR memory will be added to
the board.
– Current and voltage sensor circuits
– Voltage ramp circuits
– Electret microphone
– Audio amplifier and Delta-Sigma ADC
– PWM analog output circuit
– Audio output channel
– Up to two DVI sources and one DVI output
– Up to two 7:1 LVDS sources and one 7:1:VDS output
– Expansion header for JTAG, SPI, I 2 C and PLD I/Os
– LEDs and switches
– Standard USB cable for device programming
– RS-232/USB and JTAG/USB interface
– RoHS-compliant packaging and process
– AC adapter (international plugs)
Pre-loaded Reference Designs and Demo – The kit includes the pre-loaded Control SoC demo design that
integrates several Lattice reference designs including: the LatticeMico8 microcontroller, master WISHBONE bus
controller, soft Delta-Sigma ADC, SPI master controller, UART peripheral, Embedded Block RAM and additional
control functions.
USB connector Cable – A mini B USB port provides a communication and debug port via a USB-to-RS-232
physical channel and programming interface to the MachXO2 JTAG port.
AC Adapter (international plugs) with 5V DC output.
QuickSTART Guide – Provides information on connecting the MachXO2 Control Evaluation Board, installing
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MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Windows hardware drivers, and running the Control SoC demo.
Figure 1 shows the top side of the MachXO2 Control Evaluation Board with comments on the specific features that
are designed in the board.
Figure 1. MachXO2 Control Evaluation Board, Top Side
GSR Push-button
2x20 GPIO Header
MachXO2-1200/4000
microSD Socket
7:1 LVDS
Video Source
(Channel Link)
DVI
Video Output
DVI Video Source USB 2.0
Interface Socket
3
7:1 LVDS
Video Output
Note: The bill of materials of this board has the following limitations:
5V Power Indicator
MachXO2 DIP Switches
Electret Microphone
Speaker/Headphone Jack
AC-DC Adapter Jack
ADC Input (J9: Pin 2)
POWR1014A
JTAG Device Select (J6),
MachXO2 Position Shown
MachXO2 LED Field
Video Source 1 is available in both DVI and 7:1 LVDS interfaces. Video Source 2 is not populated.
LPDDR memory component is not populated. This feature will be populated with greater MachXO2 device density
on the board.
The initial MachXO2 device that is assembled on the board is LCMXO2-1200HC. The footprint is compatible with
greater device densities and an LCMXO2-4000HC device is planned to be populated in future versions of the
board.
Lattice Semiconductor Devices
MachXO2
This board features a 3.3V MachXO2 PLD packaged in a 132-ball csBGA package. This package allows density
migration to devices as large as 4340 LUTs. A complete description of this device can be found in the MachXO2
Family Handbook.
Power Manager II
This board also features a Power Manager II mixed-signal PLD. The POWR1014A device serves as a general-purpose
power supply monitor, reset generator, sequence controller, and high-voltage FET drivers. More information about
Power Manager II devices can be found on the Lattice web site at www.latticesemi.com/products/powermanager.

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Software Requirements
You should install the following software before you begin developing designs for the evaluation board:
Lattice Diamond 1.2 or higher
ispVM System 17.9.1 or higher
Control SoC Demonstration Design
The Control System-on-Chip (SoC) demonstration illustrates the use of the LatticeMico8 microcontroller, peripherals,
and firmware integrated to provide system control features such as power supply sequencing, voltage monitoring,
data logging to nonvolatile memory, I/O control, embedded block RAM utilization, UART communication and
PLL status monitoring.
The Power Manager II device sequences the power-up of voltage rails on the board and performs reset distribution.
LatticeMico8 executable program initializes the peripherals that are embedded in the SoC design. During initialization,
LatticeMico8 uploads the user menu on the HyperTerminal of a PC.
Users interact with LatticeMico8 and the board through the HyperTerminal of a PC.
Figure 2. Control SoC Demo Block Diagram
PC
USB/
RS232
MachXO2 Control Evaluation Board
MachXO2-1200
UART
Soft
ADC
Analog
Signal
Timer/
Counter
Master
SPI
SPI
Flash
4
LatticeMico8
Microcontroller
Embedded
Block RAM
WISHBONE Bus
LEDs/
DIP Switches
Power management is handled in two phases by the MachXO2 Control Evaluation Board system:
1. Power On – After power is supplied to the board and the 3.3V rail is stable, the POWR1014A sequences four
supply rails. Two circuits demonstrate the voltage ramp of 2N7002E power MOSFETs using the high-voltage
(HVOUT) outputs and two demonstrate power rail enable of VCC_CORE and VCCP of the MachXO2 using
digital outputs. Next, the POWR1014A asserts the MachXO2 reset. Finally, the POWR1014A enters a supply
monitoring state.
2. Post Power On – During the second phase of power management, the board’s “condition” is monitored. Power
supply rail voltage, and current is monitored by the POWR1014A. If any supply rail fails, the POWR1014A
asserts a reset for the MachXO2.
MachXO2 Function – After the reset is de-asserted, LatticeMico8 initializes the peripherals embedded in the
MachXO2 device and uploads the user menu onto the HyperTerminal window of a PC.

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 3. HyperTerminal User Menu
Users interact with LatticeMico8 microcontroller and the board by selecting the available options in the HyperTerminal
menu. The available options are:
‘m’ – This option will re-display the main menu anytime during the demonstration.
‘a’ – This option will sample the voltage in the pin #2 of header J9. By default, the node is biased at 1.65V, which
is half of the VCCIO = 3.30V. The voltage will be displayed in the HyperTerminal window. The ADC input voltage
should be limited to the range 0 to 3.0V to avoid device damage.
‘s’ – This option will read the device ID of the SPI Flash on the board and display it in the HyperTerminal. The
resulting ID is hexadecimal 0x44, which corresponds to AT25DF041A device.
‘t’ – This option samples and displays the elapsed time since the reset was de-asserted.
‘r’ - This option samples the DIP switches (reference designator SW1) on the board and displays the data in the
HyperTerminal. Users can change the DIP switches on the board and press ‘r’ to display the new value.
“0-9” – These are BCD numerical values that can be typed on the keyboard. The value will be received by
LatticeMico8, which will update the LEDs (D0-D3) on the board.
‘l’ – This is a lower case ‘L’ character. Pressing ‘l’ will sample the voltage in pin #2 of header J9 and log the data
in the SPI Flash device on the board. The WRITE page pointer will increment when ‘l’ is pressed. The initial value
of the page pointer after power-up or after a reset is 0.
‘d’ – This option will read the data from SPI Flash device and display it on the HyperTerminal window. The READ
page pointer will increment when ‘d’ is pressed. The initial value of the page pointer after power-up or after a
reset is 0.
‘c’ – This option will clear (reset) the WRITE and READ page pointers.
‘e’ – This selection will perform a bulk-erase of the Flash memory in the SPI Flash device.
Setting up the Board
Drivers and Firmware
Before you begin, you will need to obtain the necessary hardware drivers for Windows from the Lattice web site.
1. Browse to the www.latticesemi.com/MachXO2-control-kit and locate the hardware device drivers for the USB
interface.
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MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
2. Download the ZIP file to your system and unzip it to a location on your PC.
Linux Support:
The USB interface drivers for the evaluation board are included in Linux kernel 2.4.20 or greater including distributions
compatible with Lattice Diamond design software (Red Hat Enterprise v.3, v.4 or Novell SUSE Enterprise
v.10).
The Control SoC Demo is preprogrammed into the MachXO2 Control Evaluation Board, however over time it is
likely that your board will be modified.
To download the demo source files and reprogram the MachXO2 Control Evaluation Board:
1. Download demo application source code from www.latticesemi.com/mxo2-control-kit.
2. Use .\Demo_MachXO2_Control_SoC\project\control_soc_demo.jed to restore the MachXO2280 Control
SoC demo design.
3. Use .\Demo_PM_Control_BM\project\bm_demo.jed to restore the POWR1014A Board Management demo
design.
Connecting to the MachXO2 Control Evaluation Board
1. Plug the AC-DC adopter to an outlet.
2. Power the board by inserting the AC-DC adopter into the power jack with reference designator J11. Once the
connection is made, a red LED with reference designator D12 will illuminate.
3. Connect the evaluation board to your PC using the USB cable provided. The USB connector in the board has
reference designator J5.
4. If you are prompted, “Windows may connect to Windows Update”, select No, not this time from available
options and click Next to proceed with the installation.
5. Choose the Install from specific location (Advanced) option and click Next.
6. Select Search for the best driver in these locations and click the Browse button to browse to the Windows
driver folder created earlier. Select the CDM 2.04.06 WHQL Certified folder and click OK.
7. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message
indicating that the installation was successful.
Programming the PLDs
The three-pin header with reference designator J6 is used to select between the JTAG port of the MachXO2 or
POWR1014A device. Installing a jumper in pins 1 and 2 of J6 will select the JTAG port of the POWR1014A device.
Installing a jumper in pins 2 and 3 of J6 will select the JTAG port of the MachXO2 device.
Pin 1 of header J6 is marked on the silkscreen of the board with a white triangle as shown in Figure 4. This example
shows the jumper installed in pins 2 and 3 of the J6 header and the JTAG port of the MachXO2 device has been
selected.
Figure 4. J6 Header Used for Selecting the JTAG Port of the PLDs
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MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Using ispVM System software, users can scan and perform JTAG operations, including programming, with the
MachXO2 and POWR1014A devices.
Setting Up Windows HyperTerminal
You will use a terminal program to communicate with the evaluation board. The following instructions describe the
Windows HyperTerminal program which is found on most Windows PCs. You may use another terminal program if
desired although setup will be different. Windows 7 does not include HyperTerminal. Tera Term has been verified to
work with Windows 7. For Linux, Minicom is a good alternative.
Note: This step uses the procedure for Windows XP users. Steps may vary slightly if using another Windows version.
1. From the Start menu, select Control Panel > System. The “System Properties” dialog appears.
2. Select the Hardware tab and click Device Manager. The “Device Manager” dialog appears.
Figure 5. Device Manager – COM Port
3. Expand the Ports (COM & LPT) entry and note the COM port number for the USB Serial Port.
4. From the Start menu, select Programs > Accessories > Communications > HyperTerminal. The HyperTerminal
application and a “Connection Description” dialog appear.
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MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 6. New Connection – COM Port
5. Specify a Name and Icon for the new connection. Click OK. The “Connect To” dialog appears.
6. Select the COM port identified in Step 3 from the Connect using: list. Click OK.
Figure 7. Selecting the COM Port
7. The “COMn Properties” dialog appears where n is the COM port selected from the list.
8. Select the following Port Settings and click OK.
Bits per second: 115200
Data bits: 8
Parity: None
Stop bits: 1
Flow control: None
Figure 8. COM Port Properties
9. The HyperTerminal window appears.
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MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
10. From the MachXO2 Control Evaluation Board, press the reset push-button with reference designator S1. The
Control SoC demo main menu appears.
Setting Up Linux Minicom
Minicom is a terminal program found with most Linux distributions. It can be used to communicate with the
MachXO2 Control Evaluation Board.
To setup Minicom:
1. Check active serial ports:
#dmesg | grep tty
Note the tty label assigned to the USB port
2. From a command prompt, start Minicom:
#minicom –s
The configuration menu appears.
3. Highlight Serial port setup and press Enter. Serial port settings appear.
4. Press A (Serial Device). Specify the active serial device noted in Step 1 and press Enter.
5. Press E (Bps/Par/Bits). Specify 115200, None, 8 and press Enter.
6. Press F (Hardware Flow Control). Specify None and press Enter.
7. Press Esc. The configuration menu appears.
8. Select Save setup as dfl. Minicom saves the port setup as the new default.
9. Select Exit. The Minicom interface appears.
10. From the evaluation board, press the S1 push-button (GSR).The Control SoC demo main menu appears.
Ordering Information
Description Ordering Part Number
MachXO2 Control Development Kit LCMXO2-1200HC-C-EVN
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
9
China RoHS Environment-Friendly
Use Period (EFUP)

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Revision History
Date Version Change Summary
April 2011 01.0 Initial release.
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
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MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Appendix A. Schematic
Figure 9. Architecture
1
2
3
4
5
MachXO2 Control Board Architecture
7:1LVDS Conn
DVI Conn
D D
Page 11
Page 8
SPI
4Mbit
Page 12
Audio IN
7:1LVDS to DVI
Conversion
Page 12
Audio OUT
SPI Bus
ADC: Page 14
GPIO
Page 8
SD Flash
C C
DAC: Page 12
I2C Bus
7:1LVDS TX ADC-DAC
Page 4
High Voltage Drivers
Power Manager II
2x20 Header
LPDDR 128Mb
Page 8
MachXO2
GPIO
ispPAC POWR1014A
Voltage Monitor
11
Page 7
RESET SW & LEDs
7:1LVDS RX
Page 7
Page 7
Page 7
Page 13,14
Crystal
B B
SW & LEDs
Board Power
Managment
Page 4
Page 3,5
DVI to 7:1LVDS
Conversion
DVI to 7:1LVDS
Conversion
USB PORT
A UART &
A
UART
Page 6
Page 10
Page 9
JTAG Chain
Title
Architecture
Size Document Number Rev
B MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 2 of 14
1
7:1LVDS Conn
DVI Conn
7:1LVDS Conn DVI Conn
2
3
4
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MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 10. VCC33, VCC18, VCC12
1
2
3
4
5
D D
Linear VREG Step Down 5V to 3.3V Rail
AC-DC Jack - 5V
VCC5 VCC33
U11
IO19
VCC5
OUT
2
TAB 4
IN
3
C53
22uF
GND
1 DI
NCP1117ST33
C54
10uF
DI
R122
470
1
2
3
5V
Input
DI
IO20
DI
J11 PWR_JACK
DI
D12
LED
DI
C C
Linear VREG Step Down 3.3V to 1.8V Rail
Linear VREG Step Down 3.3V to 1.2V Rail
12
VCC33 VCC12 VCC_CORE VCC33
VCC33
VCC33
VCC18
U12
3
IN OUT
2
TAB
B B
GND
1 DI
C33
Q6
NCP1117ST18
10uF
BSS138LT1
PM_OUT8 [4,5]
DI
4
U17
LP3879MR_1_2
DI
1
BYPASS
OUTPUT
5
2
NC
SENSE
3
GND
4
INPUT
C106
10uF
DI
6
NC_1
7
~SD 8
R200
R81
DI 10K
DI
10K
C108
0_01uF
C66
C65
DI
9
9
10uF
22uF
DI
DI
A A
Title
Power VCC33, VCC18, VCC12
Size Document Number Rev
B MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 3 of 14
1
2
3
4
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MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 11. ispPAC-POWR1014A
1
2
3
4
5
VCC33
IO18
POWER MANAGER II
C89
C99
C107
0_1uF
0_1uF
0_1uF
DI
DI
DI
D D
U7
[5] ICC_Sense
VMON1 25
HVOUT1
VCC_CORE VCCIO33
VMON1
HVOUT1
15
HVOUT1 [7]
26
HVOUT2
VMON3
VMON2
HVOUT2
14
HVOUT2 [7]
[5] ICCIO33_Sense
27
VMON4
VMON3
[5] ICCIO18_Sense
28
PM_SMBA_OUT3
VMON5
VMON4
SMBA_OUT3
13
PM_SMBA_OUT3 [14]
32
PM_LED0
VMON6
VMON5
OUT4
12
33
PM_LED1
VMON7
VMON6
OUT5
11
34
PM_LED2
VMON8
VMON7
OUT6
10
35
PM_LED3
VMON9
VMON8
OUT7
9
[7] VMON9
36
PM_OUT8
PM_OUT8 [3,5]
VMON10
VMON9
OUT8
8
[7] VMON10
37
PM_OUT9
VMON10
OUT9
6
PM_OUT9 [5]
PM_OUT10
XO2_RESETn [7,14]
[14] PM_IN1
PM_IN1
OUT10
5
44
PM_OUT11
PM_OUT11 [14]
[14] PM_IN2
PM_IN2
IN1
OUT11
4
46
PM_OUT12
PM_OUT12 [14]
PM_IN3
IN2
OUT12
3
47
PM_OUT13
PM_OUT13 [14]
PM_IN4
IN3
OUT13
2
48
PM_OUT14
IN4
OUT14
1
PM_OUT14
PM_PLDCLK
PM_PLDCLK [7,14]
[6] PM_TDI
18 PM_MCLK
TDI
PM_MCLK [7,14]
[6] PM_TMS
C [6] PM_TCK
C
[6] PM_TDO
SCL
[7,14] SCL
SDA
[7,14] SDA
ATDI
19
TDISEL
17
16
TMS
22
TCK
21
TDO
39
SCL
38
SDA
GNDD 7
GNDD 31
GNDA 30
RESETB 40
MCLK 43
PLDCLK 42
VCCD
VCCJ
20
23
VCCPROG 24
VCCA 29
VCCD 41
VCCINP 45
ispPAC-POWR1014A
ispPAC-POWR1014A
DI
13
PM LEDs PM DIP SWITCH
Voltage Ramp Circuit
VCC33
VCC33
B VCC33
B
R195
Q5
HVOUT1
1 2N7002E
DI VMON7
1KDI
C83
PM DIP Switch
1uF
R179
DI
200
DI
RN4
SW2
RN2_4_470
DI
PM_IN3
PM_IN4
3
2
DI 10K R164
DI 10K R163
8
7
6
5
1
2
3
4
VCC33
SW DIP_2
LED LED LED LED
DI
D10 D9 D8 D7
R196
Q2
DI DI DI DI
HVOUT2
1 2N7002E
DI VMON8
PM_LED0
1KDI
PM_LED1
C35
PM_LED2
A 1uF
R198
PM_LED3
A
DI
200
DI
Title
Power ispPAC-POWR1014A
Size Document Number Rev
B MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 4 of 14
5
4
3
2
1
3
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MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 12. Power Current Sense
1
2
3
4
5
Current Sense
MachXO2 Power Rails
D D
MachXO2 - Core Current
VCC_CORE
VCC12
VCC33
VCC33
R58
C44
R232
0
DI C142
1K
DNI
R219 10uF
DI DI
220 DI
ZDT758
VCC33
0_1uF
[3,4] PM_OUT8
4
Q7A
5
DI
R59
R201
1
100
U16B
U16A
DI
DI
ICC_P
ICC_N
ICC_P
5 +
AD8604ARZ
3 +
AD8604ARZ
7
ICC_Sense [4]
1
ICC_N
6 -
2 -
IO9
IO11
C142, C143 to limit Vcc, Vccio
DI
R204
100
ramp rates to data sheet spec.
2K
R206
DI
C C
R197
MachXO2 - ICCIO33 Current
2K
DI
VCC33 VCCIO33
C41
0_01uF
DI
3
6
4
4
11
11
R67
R60 C143
1K
220 10uF
DI
DI DI
ZDT758
[4] PM_OUT9
2 Q7B
VCC33 VCC33
7 DI
R235
C46
C105
2
DI
ICCIO33_P
ICCIO33_N
0_1uF
0_1uF
IO8
IO7
DI
DI
B R191
R194
B
100
U16C
100
U16D
DI
AD8604ARZ
DI
ICCIO33_P
10 +
ICCIO18_P
12 +
AD8604ARZ
8
ICCIO33_Sense [4] 14
ICCIO18_Sense [4]
ICCIO33_N
9 -
ICCIO18_N
13 -
DI
R190
DI
R189
100
3_92K
100
3_92K
R185
DI
R184
DI
MachXO2 - ICCIO18 Current
R192
R193
3_92K
3_92K
DI
DI
VCC18 VCCIO18
C38
C91
0_01uF
0_01uF
DI
DI
R148
2
DI
ICCIO18_P
ICCIO18_N
1
14
8
4
4
11
11
IO14 IO15
A A
Title
Power Current Sense
Size Document Number Rev
B MachXO2 Control Board A
Date: Tuesday, February 22, 2011 Sheet 5 of 14
1
2
3
4
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MachXO2 Control Development Kit
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Figure 13. Configuration USB Port
1
2
3
4
5
USB Port: CPLD Configuration & USBUART Communication
VCC33
R55
4_7K
DI
D D
PM_TMS
XO2_TMS
PM_TDI
XO2_TDI
PM_TDO
XO2_TDO
PM_TCK
XO2_TCK
VCC33
VCC33
R85 R88
J6
4_7K 4_7K
1
DI DI
2
3
VCC33
Jumper_2way
DI
C144
4u7
PM_TCK
PM_TCK [4]
VCC33
R80 DI 68 XO2_TCK
XO2_TCK [7,13,14]
PM_TDI
PM_TDI [4]
XO2_TDI
XO2_TDI [13,14]
R62
0
DI PM_TDO
PM_TDO [4]
R75 0 DI
C28
R71
0
DI DI XO2_TDO
XO2_TDO [13]
10u
R76
0
DI PM_TMS
PM_TMS [4]
C VCC33
C
R87
0
DI XO2_TMS
XO2_TMS [7,13,14]
The USB interface draws no power from
the USB bus. It is self-powered.
J5 USB_MINI_B DI
VCC18FT
VBUS
VCC
Dm
1 2
Dp
SHLD_Debug C32
0_01uF DI
FT_EECS
FT_EECLK
USB_UART_TX [14]
FT_EEDATA
USB_UART_RX [14]
X3
VCC33
1
1 3
3
VBUS
2
G1 G2
4
C29
C23
18pF 12MHZ
18pF
B B
R203 R202
10k 10k
FT_EECS
FT_EECLK
FT_EEDATA
C27
0.1uF
1
D-
2
D+
3
GND 5
NC 4
R84 R89 R65 R54
R66
4_7K 4_7K 4_7K 4_7K
4_7K
DI DI DI DI
DI
C109
0_1uF
L3
DI
600ohm 500mA
U5
R86 DI 68
R38
0
DI DI
2
VCC 1S1
15
R39
0
DI
1S2
1
16
D1
5
D2 2S1
4
R70
0
DI
8
D3 2S2
6
13
D4
3S1
7
3
123SEL3S2
9
10
C145
4SEL
4S1
12
0.1uF
11
GND 4S2
14
STG3693QTR
R68 0
2k2 R56
DI
1 2
CASE
6
CASE
7
CASE
8
CASE
9
R83
0
DI
R79 100K
MH1
10
DI
MH2
11
R205
4_7K
DI
R241
10k
R249
10k
2k2 R240
2 1
1
2
R78 0 DI
U20
FT2232HL
ADBUS0
16
50
VREGIN
ADBUS1
17
ADBUS2
18
49
VREGOUT
ADBUS3
19
ADBUS4
21
ADBUS5
22
7
DM
ADBUS6
23
8
DP
ADBUS7
24
ACBUS0
26
14
RESET#
ACBUS1
27
ACBUS2
28
ACBUS3
29
6
REF
ACBUS4
30
ACBUS5
32
ACBUS6
33
ACBUS7
34
63
EECS
62
EECLK
BDBUS0
38
61
EEDATA
BDBUS1
39
BDBUS2
40
BDBUS3
41
2
OSCI
BDBUS4
43
R82
0
BDBUS5
44
BDBUS6
45
BDBUS7
46
3
OSCO
BCBUS0
48
BCBUS1
52
BCBUS2
53
13
TEST
BCBUS3
54
BCBUS4
55
BCBUS5
57
FTDI High-Speed USB BCBUS6
58
BCBUS7
59
FT2232H
PWREN#
60
SUSPEND#
36
DI
R82
0 DI
U21
CS
1
CLK
2
C126
DI
3
0.1uF
DO
93LC56-SO8
4
5
VSS
ORG
6 NU
C104
R36
0
DI
0.1uF
R37
0
DI
R61
0
DI DI
DI
R63 0
R199 12k 1%
1 2
8
VCC
7
C119
0.1uF
1
1
2
2
1
1
2
2
VCCIO 31
VCCIO 42
VCCIO 56
VCCIO 20
12
37
64
4
9
VCORE
VCORE
VCORE
VPHY
VPLL
15
1 2
2 1
2 1
2 1
2 1
GND
GND
GND
GND
GND
GND
GND
GND
AGND
1
1
1
1
5
11
15
25
35
47
51
10
2
2
2
VCC33
C30
0.1uF
cc0402
1
C85
0.1uF
cc0402
1
C82
0.1uF
cc0402
1
C48
0.1uF
cc0402
1
C31
0.1uF
cc0402
1
2
2
2
2
2
A A
Title
Configuration USB Port
Size Document Number Rev
C MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 6 of 14
1
2
3
4
5

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 14. Software, LED, Crystal, Header
1
2
3
4
5
Reset Push-Button Switch 4-DIP Switch
XO2 LEDs
D D
VCC33
VCC33 VCC33
8
7
6
5
RN1
RN2_4_470
R128
DI
S1
10K
R127 R126 R125 R124
10K 10K 10K 10K
XO2 Global Reset
DI
DI DI DI DI SW1 CT1934MS-ND
[4,14] XO2_RESETn
[14] SW0
SW0
1
8
1 4
[14] SW1
SW1
2
7
LED LED LED LED
[14] SW2
SW2
3
6
D4 D3 D2 D1
C63
[14] SW3
S SWW
3
4
5
DI DI DI DI
0_1uF
DI
C SWDIP_4 SWDIP_4
C
[14] XO2_LED0
XO2_LED0
2 3
[14] XO2_LED1
XO2_LED1
DI
[14] XO2_LED2
XO2_LED2
DI
[14] XO2_LED3
XO2_LED3
1
2
3
4
IO3
16
2x20 Header 24 MHz Crystal
X_1 [14]
X_1
VCC18
HCM49 24.000MABJ-UT
VCC12 VCC33
J4
R2 IO2
X2
1M
1 2 XO2_ADC_IN
DI
XO2_ADC_IN [14]
B 3 4
1 2
X_2
X_2 [14]
B
5 6 XO2_GPIO_11
XO2_GPIO_11 [14]
[14] XO2_GPIO_0
XO2_GPIO_0 7 8
[14] XO2_GPIO_1
XO2_GPIO_1 9 10
HVOUT1
HVOUT1 [4]
C4
C11
[14] XO2_GPIO_2
XO2_GPIO_2 11 12
12pF
12pF
[14] XO2_GPIO_3
XO2_GPIO_3 13 14
HVOUT2
HVOUT2 [4]
DI
DI
[14] XO2_GPIO_4
XO2_GPIO_4 15 16
PM_OUT14
PM_OUT14
DI
[14] XO2_GPIO_5
XO2_GPIO_5 17 18
PM_PLDCLK
PM_PLDCLK [4,14]
[14] XO2_GPIO_6
XO2_GPIO_6 19 20
PM_MCLK
PM_MCLK [4,14]
[14] XO2_GPIO_7
XO2_GPIO_7 21 22
[13] TDO_HDR
23 24
SCL
SCL [4,14]
[13] TDI_HDR
25 26
SDA
VCC33
SDA [4,14]
[6,13,14] TMS_HDR
XO2_GPIO_10
25 MHz OSC
27 28
XO2_GPIO_10 [14]
[6,13,14] TCK_HDR
29 30 XO2_GPIO_9
XO2_GPIO_9 [14]
R1 10K DI
31 32 XO2_GPIO_8
XO2_GPIO_8 [14]
[4] VMON9
VMON9 33 34
XO2_SPI_CLK
XO2_SPI_IN
XO2_SPI_CLK [8,14]
35 36
[4] VMON10
VMON10
XO2_SPI_OUT
XO2_SPI_IN [8,14]
X1
37 38
XO2_SPI_OUT [8,14]
39 40
1
EOH
VCC
2
CON40A
GND
DNI
2x20x100mil
CTS-CB3LV-3C-25MHz
A A
4
R4
1K
OUTPUT
3
C8
0_1uF
DI
DI
R4
1K DI
R3
0
DNI
Title
SW, LED, Crystal, Header
Size Document Number Rev
B MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 7 of 14
1
2
3
4
5

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 15. Memory LPDDR, SD, SPI
1
2
3
4
5
LPDDR - 128Mb (4 Meg x 4 banks x 8 data)
4MBit SPI
D D
VCC18
VCC33
Package: SOIC8 (WIDE)
XO2_SPI_CS0
C71
C79
XO2_SPI_CLK
XO2_SPI_CS0 [14]
0_001uF
0_1uF
XO2_SPI_IN
XO2_SPI_CLK [7,14]
DI
DI
XO2_SPI_OUT
XO2_SPI_IN [7,14]
XO2_SPI_OUT [7,14]
LPDDR_A0
VCC33
[14] LPDDR_A0
LPDDR_A1
LPDDR_DQ0
[14] LPDDR_A1
LPDDR_A2
LPDDR_DQ1
LPDDR_DQ0 [14]
[14] LPDDR_A2
LPDDR_A3
LPDDR_DQ2
LPDDR_DQ1 [14]
U15
[14] LPDDR_A3
LPDDR_A4
LPDDR_DQ3
LPDDR_DQ2 [14]
XO2_SPI_CS0
[14] LPDDR_A4
LPDDR_A5
LPDDR_DQ4
LPDDR_DQ3 [14]
S
XO2_SPI_CLK
[14] LPDDR_A5
LPDDR_A6
LPDDR_DQ5
LPDDR_DQ4 [14]
XO2_SPI_IN
[14] LPDDR_A6
LPDDR_A7
LPDDR_DQ6
LPDDR_DQ5 [14]
C C
XO2_SPI_OUT
[14] LPDDR_A7
LPDDR_A8
LPDDR_DQ7
LPDDR_DQ6 [14]
[14] LPDDR_A8
LPDDR_A9
LPDDR_DQ7 [14]
[14] LPDDR_A9
9 8
AT25DF041A-MH-B
LPDDR_A10
[14] LPDDR_A10
10 7
LPDDR_A11
VCC18
[14] LPDDR_A11
11 6
LPDDR_A12
[14] LPDDR_A12
12 5
13 4
Package: UDFN
LPDDR_CK
[14] LPDDR_CK
14 3
LPDDR_CKn
[14] LPDDR_CKn
15 2
LPDDR_CKE
[14] LPDDR_CKE
16 1
RN3 RN1_8_10K DI
LPDDR_CSn
[14] LPDDR_CSn
R158 10K DI
LPDDR_RASn
[14] LPDDR_RASn
LPDDR_CASn
[14] LPDDR_CASn
LPDDR_BA0
[14] LPDDR_BA0
LPDDR_BA1
LPDDR_LDM
[14] LPDDR_BA1
LPDDR_LDQS
LPDDR_LDM [14]
LPDDR_WEn
LPDDR_LDQS [14]
[14] LPDDR_WEn
Lower Byte Mask & Strobe
Micro SD Card Socket
VCC33
B B
uSD_DAT2
[14] uSD_DAT2
uSD_DAT3
[14] uSD_DAT3
uSD_CMD
[14] uSD_CMD
uSD_CLK
[14] uSD_CLK
uSD_DAT0
[14] uSD_DAT0
uSD_DAT1
[14] uSD_DAT1
LPDDR_DQ0 9 8
VCC18
LPDDR_DQ1 10 7
LPDDR_DQ2 11 6
LPDDR_DQ3 12 5
LPDDR_DQ4 13 4
LPDDR_DQ5 14 3
LPDDR_DQ6 15 2
LPDDR_DQ7 16 1
RN2 RN1_8_10K DNI
1
Q 2
8
Vcc
3
W D
4
Vss
5
C 6
7
Reset
U1
1
DAT2
VDD
2
CD/DAT3
3
CMD
5
CLK
7
DAT0
8
DAT1
microSD Socket Socket
4
VSS 6
J8
A0
J9
A1
DQ0
K7
A2
K8
A3
K2
A4
K3
A5
J1
A6
J2
A7
J3
A8
H1
A9
J7
A10
H2
A11
H3
A12
G2
CK
G3
CK#
G1
CKE
H7
CS#
G9
RAS#
G8
CAS#
H8
BA0
H9
BA1
G7
WE#
MT46H16M16LFBF
U6
A8
DQ1 B7
DQ10 D3
DQ11 C2
DQ12 C3
DQ13 B2
DQ14 B3
DQ15 A2
DQ2 B8
DQ3 C7
DQ4 C8
DQ5 D7
DQ6 D8
DQ7 E7
DQ8 E3
DQ9 D2
LDM F8
LDQS E8
UDM F2
UDQS E2
D9
NC
NC
F3 NC
U14
S
AT25DF041A-SH-B
R159 10K DI
F7
C81
0_1uF
DI
1
Q 2
8
Vcc
3
W D
4
Vss
5
C 6
C72 C75
7
0_01uF 0_1uF
Reset
DI DI
C74
0_1uF
DI
R186
0
DI
VDD A9
VDD F9
VDD K9
VDDQ A7
VDDQ B1
VDDQ C9
VDDQ D1
VDDQ E9
17
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
A1
F1
K1
A3
B9
C1
E1
Empty External Pull-UP resistors. The internal XO2 resistors are used for bias.
A A
Title
Memory LPDDR, SD, SPI
Size Document Number Rev
B MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 8 of 14
1
2
3
4
5

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 16. Video Input 1
1
2
3
4
5
Video Input Source 1 : DVI or MDR for direct 7:1LVDS
Resistor MUX
DVI Connector DVI - TMDS Decoder LVDS Translator
R
TXIN1_1
TXIN0_1
TMDS_1_DATA2_P
TXIN17_1
D D
TMDS_1_DATA2_N
TXIN16_1
TMDS_1_DATA2_N
TXIN11_1
TMDS_1_DATA2_P
TI_AVDD_1
TXIN10_1
TXIN5_1
TXIN27_1
TMDS_1_DATA1_P
TMDS_1_DATA1_N
DDC_CLK
DDC_DATA
DDC_CLK
DDC_DATA
[10,11]
[10,11]
TMDS_1_DATA0_P
TXIN27_1
TX_OUT0_N_1
TX_OUT0_N_1
TMDS_1_DATA0_N
TXIN26_1
TX_OUT0_P_1
TX_OUT0_P_1
XO2_IN0_1_N [14]
G
TXIN3_1
TXIN25_1
XO2_IN0_1_P [14]
TXIN2_1
TXIN24_1
TX_OUT1_N_1
TX_OUT1_N_1
TXIN24_1
TXIN23_1
TX_OUT1_P_1
TX_OUT1_P_1
XO2_IN1_1_N [14]
TMDS_1_DATA1_N
TMDS_1_CLK_P
TXIN22_1
TXIN22_1
XO2_IN1_1_P [14]
TMDS_1_DATA1_P
TMDS_1_CLK_N
TXIN21_1
TXIN21_1
TX_OUT2_N_1
TX_OUT2_N_1
TXIN20_1
TXIN20_1
TX_OUT2_P_1
TX_OUT2_P_1
XO2_IN2_1_N [14]
TXIN19_1
TXIN19_1
XO2_IN2_1_P [14]
TXIN23_1
TXIN18_1
TX_OUT3_N_1
TX_OUT3_N_1
TXIN17_1
TX_OUT3_P_1
TX_OUT3_P_1
XO2_IN3_1_N [14]
TXIN16_1
XO2_IN3_1_P [14]
[14]
DVDD_1
TXIN15_1
TX_CLKOUT_N_1
TX_CLKOUT_N_1
Hot_Plug_Video
TXIN14_1
TX_CLKOUT_P_1
TX_CLKOUT_P_1
XO2_CLKIN_1_N [14]
Hot_Plug_Video
TXIN13_1
XO2_CLKIN_1_P [14]
OCK_INV_1
TXIN12_1
NS_LVCC_1
DFO_1
TXIN11_1
PIXS_1
TXIN10_1
STAGN_1
TXIN9_1
ST_1
TXIN8_1
LVDSGND B
TXIN6_1
TXIN7_1
PDN_1
TXIN4_1
TXIN6_1
NS_PVCC_1
TMDS_1_DATA0_N
PDON_1
TXIN13_1
TXIN5_1
TMDS_1_DATA0_P
TXIN12_1
TXIN4_1
C TXIN9_1
TXIN3_1
C
DVDD_1
TXIN8_1
TXIN2_1
TXIN26_1
TXIN1_1
TXIN25_1
TXIN0_1
NS_STB_1
TXCLKIN_1
DVDD_1
MDR_TX_OUT0_N_1
MDR_TX_OUT0_P_1
TMDS_1_CLK_P
PWRDWN_1
MDR_TX_OUT1_N_1
TMDS_1_CLK_N
MDR_TX_OUT1_P_1
TI_OVDD_1
MDR_TX_OUT2_N_1
MDR_TX_OUT2_P_1
TXCLKIN_1
DS90CR287 U19
MDR_TX_OUT3_N_1
MDR_TX_OUT3_P_1
CTL3_1
CTL2_1
MDR_TX_CLKOUT_N_1
CTL1_1
MDR_TX_CLKOUT_P_1
TXIN18_1
TXIN15_1 IO5
TI_PVDD_1
TXIN14_1
SCDT_1
43
TxOUT3N
TxOUT3P
37
38
TxOUT2N
TxOUT2P
41
42
TxOUT1N
TxOUT1P
45
46
TxOUT0N
TxOUT0P
47
48
LVDSVCC 44
LVDSGND 36
LVDSGND 49
TxCLKOUTN
TxCLKOUTP
39
40
50
TxIN27
30
TxIN26
28
TxIN25
27
TxIN24
25
TxIN23
24
TxIN22
23
TxIN21
22
TxIN20
20
TxIN19
19
TxIN18
18
TxIN17
16
TxIN16
15
TxIN15
14
TxIN14
12
TxIN13
11
TxIN12
10
TxIN11
8
TxIN10
7
TxIN9
6
TxIN8
4
TxIN7
3
TxIN6
2
TxIN5
56
TxIN4
55
TxIN3
54
TxIN2
52
TxIN1
51
TxIN0
32
PWRDWN
GND 53
GND 21
GND 29
VCC 1
GND 5
PLLGND 35
GND 13
PLLVCC 34
PLLGND 33
VCC 9
VCC 17
VCC 26
79
AGND
QE23
37
QE22
36
80
Rx2P
QE21
35
81
Rx2N R-in
QE20
34
QE19
33
82
AVDD
QE18
32
83
AGND
QE17
31
84
AVDD
QE16
30
85
Rx1P
QO23
77
86
Rx1N G-in
QO22
75
QO21
74
87
AGND
QO20
73
88
AVDD
QO19
72
89
AGND
QO18
71
QO17
70
90
Rx0P
QO16
69
91
Rx0N B-in
QE15
27
92
AGND
QE14
26
QE13
25
93
RxCP
QE12
24
94
RxCN Clk-in
QE11
23
QE10
22
95
AVDD
QE9
21
QE8
20
96
EXT_RES
QO15
66
99
RSVD (Tie high)
QO14
65
QO13
64
QO12
63
100
OCK_INV
QO11
62
1
DFO
QO10
61
4
PIXS
QO9
60
7
STAGN
QO8
59
3
ST
QE7
17
2
PDN
QE6
16
9
PDON
QE5
15
QE4
14
QE3
13
QE2
12
QE1
11
QE0
10
QO7
56
31
TxCLKIN
QO6
55
QO5
54
QO4
53
QO3
52
QO2
51
QO1
50
QO0
49
CTL3
42
CTL2
41
CTL1
40
DE
46
HSYNC 48
ODCK
44
VSYNC 47
DVI-Integrated
DVI-Integrated
TMDS_Data2-
1
TMDS_Data2+
2
TMDS_Data2/4_Shield
3
TMDS_Data4-
4
TMDS_Data4+
5
DDC_Clock
6
DDC_Data
7
Analog_Vertical_Sync
8
R229 0 DI
R228 0 DI
TMDS_Data1-
9
TMDS_Data1+
10
TMDS_Data1/3_Shield
11
R223 0 DI
R222 0 DI
TMDS_Data3-
12
TMDS_Data3+
13
+5V_Power
14
GND(for +5V)
15
R248 0 DI
Hot_Plug_Detect
16
TMDS_Data0-
17
TMDS_Data0+
18
TMDS_Data0/5_Shield
19
6
DVDD
38
DVDD
TMDS_Data5-
20
67
DVDD
TMDS_Data5+
21
5
DGND
TMDS_Clock_Shield
22
39
DGND
68
DGND
R216 0 DNI
TMDS_Clock+
23
R215 0 DNI
TMDS_Clock-
24
18
OVDD
29
OVDD
43
OVDD
57
OVDD
78
R210 0 DNI
OVDD
Analog_Red
19
OGND
28
R212 0 DNI
OGND
45
R211 0 DNI
OGND
58
OGND
76
OGND
97
PVDD
DVI_I J2
98
PGND
SCDT
8
C1
Analog_Green C2
Analog_Blue C3
Analog_Horizontal_Sync C4
Analog_Ground_1 C5
Analog_Ground_2 C6
R231 0 DI
R230 0 DI
R227 0 DI
R226 0 DI
R225 0 DI
R224 0 DI
R218 0 DNI
R217 0 DNI
R214 0 DNI
R213 0 DNI
R209 0 DNI
IO4
R-even
R-odd
G-even
G-odd
B-even B-even
B-odd
18
TFP401A U2
B B
Supporting Circuits
MDR Connector
J1
MDR_TX_OUT0_N_1
DVDD_1
TXIN7_1 CTL1_1
MDR_TX_OUT0_P_1
VCC33
CTL2_1
LED will be ON
VCC33
when link is
MDR_TX_OUT1_N_1
R5 0 DNI CTL3_1
active.
TI_PVDD_1
TI_AVDD_1
(SCDT high)
MDR_TX_OUT1_P_1
C125
MDR_TX_OUT2_N_1
DVDD_1 R21 10K DI OCK_INV_1
0_001uF
MDR_TX_OUT2_P_1
PDN_1
3
DI
R18 10K DI PDON_1
Q1
SCDT_1
BSS138LT1
NS_LVCC_1
PWRDWN_1
DVDD_1
MDR_TX_CLKOUT_N_1
1 2
C19
NS_STB_1
C115
MDR_TX_CLKOUT_P_1
0_1uF
0_1uF
DI
DFO_1
DI
DDC_+5VDC
MDR_TX_OUT3_N_1
RxIn3-
15
PIXS_1
RxIn3Gnd
2
MDR_TX_OUT3_P_1
TOP Package View
NS_PVCC_1
RxIn3+
14
STAGN_1
TI_OVDD_1
DDC_Gnd_1
1
(3) Drain
C15
ST_1
0_01uF
OCK_INV_1
DI
SOT-23
NS_STB_1
A A
(1) Gate (2) Source
10226-1A10PE-ND
3
USB_+5VDC 16
DDC_Gnd_26
26
RxIn0-
13
RxIn0Gnd
25
RxIn0+
12
Sense
24
USB/DDC_Gnd
11
RxIn1-
23
RxIn1Gnd
10
RxIn1+
22
DDC/SDA
9
RxIn2-
21
RxIn2Gnd
8
RxIn2+
20
USB+
7
USB_Shield
19
USB-
6
DDC/SCL
18
RxClkIn-
5
RxClkInGnd
17
RxClkIn+
4
Mounting_R 27
R27 DI
470
R8 0 DNI
R6 0 DI
D5
LED_Green
C140 C141 C136 C135
C122 C123 C124
10uF 0_1uF 0_01uF 0_001uF
10uF 0_1uF 0_01uF
DI DI DI DI
R20 10K DI
DI DI DI
R233 10K DI
C20
C18 C17
R236 10K DI
C121
C6 C137
10uF
0_01uF 0_001uF
10uF
0_01uF 0_001uF
DI
DI DI
R244 10K DI
DI
DI DI
R19 10K DI
R239 10K DI
C22 C112
C14
R242 10K DI
C21 C16 C5 C113
10uF 0_1uF
0_001uF
R22 10K DNI
10uF 0_1uF 0_01uF 0_001uF
DI DI
DI
Mounting_L
28
DI DI DI DI
R237 10K DNI
ODCK opposite edge from Video Source 2
Channel Link - RX
A
Title
Video Input 1
Size Document Number Rev
C MachXO2 Control Board
Date: Tuesday, February 15, 2011 Sheet 9 of 14
1
2
3
4
5

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 17. Video Input 2
1
2
3
4
5
Video Input Source 2 : DVI or MDR for direct 7:1LVDS
Resistor MUX
DVI Connector DVI - TMDS Decoder LVDS Translator
R
TXIN1_2
DVI-Integrated
DVI-Integrated
TXIN0_2
TMDS_2_DATA2_P
TXIN17_2
TMDS_2_DATA2_N
TXIN16_2
D D
TMDS_2_DATA2_N
TXIN11_2
TMDS_Data2-
1
TMDS_2_DATA2_P
TI_AVDD_2
TXIN10_2
TMDS_Data2+
2
TXIN5_2
TXIN27_2
TMDS_Data2/4_Shield
3
TMDS_2_DATA1_P
TMDS_Data4-
4
TMDS_2_DATA1_N
TMDS_Data4+
5
DDC_CLK
DDC_Clock
6
DDC_DATA
DDC_CLK
DDC_Data
7
DDC_DATA
[9,11]
Analog_Vertical_Sync
8
[9,11]
TMDS_2_DATA0_P
TXIN27_2
TX_OUT0_N_2
TX_OUT0_N_2
TMDS_2_DATA0_N
TXIN26_2
TX_OUT0_P_2
TX_OUT0_P_2
XO2_IN0_2_N [14]
G
TXIN3_2
TXIN25_2
XO2_IN0_2_P [14]
TXIN2_2
TXIN24_2
TX_OUT1_N_2
TX_OUT1_N_2 R221 0 DI
TXIN24_2
TXIN23_2
TX_OUT1_P_2
TX_OUT1_P_2
XO2_IN1_2_N [14]
TMDS_2_DATA1_N
TMDS_2_CLK_P
TXIN22_2
TXIN22_2
XO2_IN1_2_P [14]
TMDS_Data1-
9
TMDS_2_DATA1_P
TMDS_2_CLK_N
TXIN21_2
TXIN21_2
TX_OUT2_N_2
TX_OUT2_N_2
TMDS_Data1+
10
TXIN20_2
TXIN20_2
TX_OUT2_P_2
TX_OUT2_P_2 R107 0 DI
XO2_IN2_2_N [14]
TXIN19_2
TXIN19_2
XO2_IN2_2_P [14]
TMDS_Data1/3_Shield
11
TXIN23_2
TXIN18_2
TX_OUT3_N_2
TX_OUT3_N_2
TXIN17_2
TX_OUT3_P_2
TX_OUT3_P_2
XO2_IN3_2_N [14]
TMDS_Data3-
12
TXIN16_2
XO2_IN3_2_P [14]
TMDS_Data3+
13
[14]
DVDD_2
TXIN15_2
TX_CLKOUT_N_2
TX_CLKOUT_N_2
Hot_Plug_Video
TXIN14_2
TX_CLKOUT_P_2
TX_CLKOUT_P_2
XO2_CLKIN_2_N [14]
+5V_Power
14
Hot_Plug_Video
TXIN13_2
XO2_CLKIN_2_P [14]
GND(for +5V)
15
OCK_INV_2
TXIN12_2
NS_LVCC_2
DFO_2
TXIN11_2
Hot_Plug_Detect
16
PIXS_2
TXIN10_2
STAGN_2
TXIN9_2
ST_2
B
TXIN8_2
TXIN6_2
TXIN7_2
PDN_2
TXIN4_2
TXIN6_2
NS_PVCC_2
TMDS_2_DATA0_N
PDON_2
TXIN13_2
TXIN5_2
TMDS_Data0-
17
TMDS_2_DATA0_P
TXIN12_2
TXIN4_2
TMDS_Data0+
18
TXIN9_2
TXIN3_2
C DVDD_2
TXIN8_2
TXIN2_2
C
TMDS_Data0/5_Shield
19
TXIN26_2
TXIN1_2
TXIN25_2
TXIN0_2
TMDS_Data5-
20
NS_STB_2
TMDS_Data5+
21
TXCLKIN_2
DVDD_2
MDR_TX_OUT0_N_2
MDR_TX_OUT0_P_2
TMDS_Clock_Shield
22
TMDS_2_CLK_P
PWRDWN_2
MDR_TX_OUT1_N_2
TMDS_Clock+
23
TMDS_2_CLK_N
MDR_TX_OUT1_P_2
TMDS_Clock-
24
TI_OVDD_2
MDR_TX_OUT2_N_2
MDR_TX_OUT2_P_2
TXCLKIN_2
MDR_TX_OUT3_N_2
MDR_TX_OUT3_P_2
Analog_Red
CTL3_2
CTL2_2
MDR_TX_CLKOUT_N_2
CTL1_2
MDR_TX_CLKOUT_P_2
TXIN18_2
TXIN15_2
TI_PVDD_2
TXIN14_2
DVI_I J10
SCDT_2
C1
Analog_Green C2
Analog_Blue C3
Analog_Horizontal_Sync C4
Analog_Ground_1 C5
Analog_Ground_2 C6
79
AGND
QE23
37
QE22
36
80
Rx2P
QE21
35
81
Rx2N R-in
QE20
34
QE19
33
82
AVDD
QE18
32
83
AGND
QE17
31
84
AVDD
QE16
30
85
Rx1P
QO23
77
86
Rx1N G-in
QO22
75
QO21
74
87
AGND
QO20
73
88
AVDD
QO19
72
89
AGND
QO18
71
QO17
70
90
R112 0 DI
Rx0P
QO16
69
91
R111 0 DI
Rx0N B-in
QE15
27
92
AGND
QE14
26
QE13
25
93
RxCP
QE12
24
94 Clk-in
R108 0 DI
RxCN
QE11
23
QE10
22
95
AVDD
QE9
21
QE8
20
96
EXT_RES
QO15
66
99
R95 0 DI
RSVD (Tie high)
QO14
65
R93 0 DI
QO13
64
QO12
63
100
OCK_INV
QO11
62
1
DFO
QO10
61
4
PIXS
QO9
60
7
STAGN
QO8
59
3
ST
QE7
17
2
PDN
QE6
16
9
PDON
QE5
15
QE4
14
QE3
13
QE2
12
QE1
11
QE0
10
R113 0 DNI
QO7
56
R110 0 DNI
QO6
55
QO5
54
R208 0 DNI
QO4
53
QO3
52
QO2
51
R109 0 DNI
QO1
50
R106 0 DNI
QO0
49
R98 0 DNI
CTL3
42
R96 0 DNI
CTL2
41
CTL1
40
DE
46
HSYNC 48
ODCK
44
VSYNC 47
R220 0 DI
R99 0 DI
LVDSGND
6
DVDD
38
DVDD
67
DVDD
5
DGND
39
DGND
68
DGND
18
OVDD
29
OVDD
43
OVDD
57
OVDD
78
DS90CR287 U18
R104 0 DNI
OVDD
19
OGND
28
OGND
45
OGND
58
OGND
76
OGND
97
PVDD
98
PGND
SCDT
8
43
TxOUT3N
TxOUT3P
37
38
TxOUT2N
TxOUT2P
41
42
TxOUT1N
TxOUT1P
45
46
TxOUT0N
TxOUT0P
47
48
LVDSVCC 44
LVDSGND 36
LVDSGND 49
TxCLKOUTN
TxCLKOUTP
39
40
50
TxIN27
30
TxIN26
28
TxIN25
27
TxIN24
25
TxIN23
24
TxIN22
23
TxIN21
22
TxIN20
20
TxIN19
19
TxIN18
18
TxIN17
16
TxIN16
15
TxIN15
14
TxIN14
12
TxIN13
11
TxIN12
10
TxIN11
8
TxIN10
7
TxIN9
6
TxIN8
4
TxIN7
3
TxIN6
2
TxIN5
56
TxIN4
55
TxIN3
54
TxIN2
52
TxIN1
51
TxIN0
32
PWRDWN
GND 53
GND 21
GND 29
VCC 1
GND 5
PLLGND 35
GND 13
PLLVCC 34
PLLGND 33
VCC 9
VCC 17
VCC 26
R102 0 DI
R247 0 DI
31
TxCLKIN
R207 0 DNI
R92 0 DNI
IO17
IO16
R-even
R-odd
G-even
G-odd
B-even
B-odd
19
TFP401A U9
Supporting Circuits
MDR Connector
B B
J13
TXIN7_2 R105 0 DNI CTL1_2
R114 DI
MDR_TX_OUT0_N_2
R103 0 DI CTL2_2
DVDD_2 470
MDR_TX_OUT0_P_2
CTL3_2
VCC33
LED will be ON
VCC33
when link is
MDR_TX_OUT1_N_2
active.
TI_PVDD_2
DVDD_2
OCK_INV_2
TI_AVDD_2
(SCDT high)
MDR_TX_OUT1_P_2
C133 C138
R119 10K DI PDN_2
C128 C130
MDR_TX_OUT2_N_2
0_1uF 0_01uF
R115 10K DI PDON_2
0_1uF 0_01uF
DI DI
MDR_TX_OUT2_P_2
3
DI DI
R94 10K DI PWRDWN_2
Q8
R97 10K DI NS_STB_2
SCDT_2
BSS138LT1
NS_LVCC_2
DVDD_2
MDR_TX_CLKOUT_N_2
1 2
C43 C42 C40 C39
C116 C34
MDR_TX_CLKOUT_P_2
R120 10K DI DFO_2
10uF 0_1uF 0_01uF 0_001uF
0_1uF 0_01uF
DI DI DI DI
R117 10K DI PIXS_2
DI DI
DDC_+5VDC
MDR_TX_OUT3_N_2
RxIn3-
15
R116 10K DI STAGN_2
TOP Package View
RxIn3Gnd
2
MDR_TX_OUT3_P_2
NS_PVCC_2
RxIn3+
14
ST_2
(3) Drain
TI_OVDD_2
DDC_Gnd_1
1
C110 C36 C37
C118 C45
C114
R243 10K DNI OCK_INV_2
0_1uF 0_01uF 0_001uF
SOT-23
10uF 0_1uF
0_001uF
DI DI DI
R101 10K DNI NS_STB_2
DI DI
DI
A (1) Gate (2) Source
A
3
USB_+5VDC 16
DDC_Gnd_26
26
RxIn0-
13
RxIn0Gnd
25
RxIn0+
12
Sense
24
USB/DDC_Gnd
11
RxIn1-
23
RxIn1Gnd
10
RxIn1+
22
DDC/SDA
9
RxIn2-
21
RxIn2Gnd
8
RxIn2+
20
USB+
7
USB_Shield
19
USB-
6
DDC/SCL
18
RxClkIn-
5
RxClkInGnd
17
RxClkIn+
4
Mounting_R 27
R100 0 DNI
D11
LED_Green
R121 10K DI
C129
C131
C127
C132
10uF
0_001uF
10uF
0_001uF
DI
DI
DI
DI
C120
C139
10uF
0_001uF
DI
DI
R118 10K DI
C111
C117
10uF
0_01uF
DI
Mounting_L
28
DI
10226-1A10PE-ND
Channel Link - RX
Title
Video Input 2
Size Document Number Rev
C MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 10 of 14
1
2
3
4
5

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 18. Video Output
1
2
3
4
5
Video Output : DVI or MDR for direct 7:1LVDS
TMDS - DVI Connector
TMDS - DVI Decoder
LVDS Translator
Resistor De-MUX
RX_IN0_N
VCC5
[14] XO2_OUT0_N
U3
RX_IN0_N
RXOUT27
RXOUT1
RX_IN0_P
RXOUT26
RXOUT0
TMDS_DATA2_N
RXOUT25
RXOUT17
TMDS_DATA2_P
TMDS_DATA2_P
D D
RX_IN0_P
RX_IN1_N
RXOUT24
RXOUT16
TMDS_DATA2_N
[14] XO2_OUT0_P
R/HVSync
RX_IN1_P
RXOUT23
RXOUT11
DI 0 R 1 2
RX_IN1_N
RXOUT22
RXOUT10
TI_TVDD
[14] XO2_OUT1_N
RX_IN2_N
RXOUT21
RXOUT5
RX_IN2_P
RXOUT20
RXOUT27
TMDS_DATA1_P
R245 10K DNI
RXOUT19
RXOUT3
G/CTL1
TMDS_DATA1_N
RX_IN3_N
RXOUT18
RXOUT2
DDC_CLK
RX_IN3_P
RXOUT17
RXOUT24
DDC_CLK
DDC_DATA
RXOUT16
RXOUT22
DDC_DATA
RX_IN1_P
RX_CLKIN_N
RXOUT15
TMDS_DATA0_P
[9,10]
[14] XO2_OUT1_P
RX_CLKIN_P
RXOUT14
RXOUT21
TMDS_DATA0_N
[9,10]
B/CTL3:2
RX_IN2_N
RXOUT13
RXOUT20
[14] XO2_OUT2_N
PWRDWN
RXOUT12
RXOUT19
RXOUT11
RXOUT23
NS_LVCC
RXOUT10
RXOUT6
TMDS_CLK_P
RXOUT9
RXOUT4
Clk Out
TMDS_CLK_N
TMDS_DATA1_N
RXOUT8
RXOUT13
TMDS_DATA1_P
RXOUT7
RXOUT12
RX_IN2_P
RXOUT6
RXOUT9
TI_TVDD
[14] XO2_OUT2_P
RXOUT5
RXOUT8
RX_IN3_N
NS_PVCC
RXOUT4
RXOUT26
[14] XO2_OUT3_N
RXOUT3
RXOUT25
RXOUT2
RXOUT1
RXCLKOUT
57
TI_PVDD
RXOUT0
IDCKP
56
NS_DVDD
IDCKN
C134
RXCLKOUT
RXOUT18
[14]
2
RX_IN3_P
DE
0_1uF
Hot_Plug_Video
[14] XO2_OUT3_P
RXOUT15
DVDD DI
RX_CLKIN_N
RXOUT14
[14] XO2_CLKOUT_N
VREF
TMDS_DATA0_N
EDGE
TMDS_DATA0_P
DKEN
RX_CLKIN_P
[14] XO2_CLKOUT_P
C ISEL
13
C
ISEL/RSTN
CTL3
CTL2
CTL1
N/C
TMDS_CLK_P
MDR_RX_IN0_N
BSEL
MSEN
TMDS_CLK_N
MDR_RX_IN0_P
DSEL
14
DSEL/SDA
MDR_RX_IN1_N
PDN
10
MDR_RX_IN1_P
PDN
DNI 0 R 1 7 2 MDR_RX_IN2_N
MDR_RX_IN2_P
TFP410
MDR_RX_IN3_N
MDR_RX_IN3_P
MDR_RX_CLKOUT_N
MDR_RX_CLKOUT_P
49
TXCN
35
DKEN
RESERVED (Tie to GND)
34
15
BSEL/SCL
21
TVDD
TXCP
22
23
TX0N 24
TGND
TX0P
25
26
TX1N 27
TVDD
TX1P
28
29
TX2N 30
TGND
TX2P
31
32
62
DATA1
MSEN/PO1
11
DATA2
61 DATA3
60 DATA4
59 DATA5
58 DATA6
55 DATA7
54 DATA8
53 DATA9
52 DATA10
51 DATA11
47
DATA12
50
DATA13
46 DATA14
45 DATA15
44 DATA16
43 DATA17
42 DATA18
41 DATA19
40 DATA20
39 DATA21
38 DATA22
37 DATA23
36
TGND 20
TFADJ
19
5
VSYNC
4
HSYNC
3
VREF
9
EDGE/HTPLG
DGND
6
CTL3/A3/DK3
7
CTL2/A2/DK2
8
CTL1/A1/DK1
16
DGND 48
DVDD 33
DGND 64
DVDD 1
DVDD 12
PVDD 18
PGND 17
R246 10K DNI
20
RxIN3P
DI 0 R 1 7 1
14
DI 0 R 1 7 4
LVDSGND
R31 510, 1%
63
SM_R_0603
DATA0
R129
100
SM_R_0603
DS90CR288A U10
DNI 0 R 1 6 8
DNI 0 R 1 1
DNI 0 R 1 5
RxIN3N
16
RxIN2P
19
RxIN2N
12
RxIN1P
15
RxIN1N
10
RxIN0P
11
RxIN0N
9
18
RxCLKINP
13
LVDSVCC
8
LVDSGND
21
LVDSGND
RxCLKINN
DI 0 R 1 7 0
J3
DVI-Integrated
R135
100
RxOUT27
7
SM_R_0603
RxOUT26
6
1
TMDS_Data2-
RxOUT25
5
2
DI 0 R 1 6 7
TMDS_Data2+
RxOUT24
3
RxOUT23
2
3
TMDS_Data2/4_Shield
RxOUT22
1
RxOUT21
55
4
TMDS_Data4-
RxOUT20
54
5
R130
TMDS_Data4+
RxOUT19
53
100
RxOUT18
51
6
SM_R_0603
DDC_Clock
RxOUT17
50
7
DDC_Data
RxOUT16
49
DI 0 R 9
17
RxOUT15
47
8
Analog_Vertical_Sync
RxOUT14
46
RxOUT13
45
25
PWRDWN RxOUT12
43
RxOUT11
42
R134
RxOUT10
41
100
RxOUT9
39
9
SM_R_0603
TMDS_Data1-
RxOUT8
38
10
TMDS_Data1+
RxOUT7
37
RxOUT6
35
11
TMDS_Data1/3_Shield
RxOUT5
34
DI 0 R 1 7
23
PLLVCC RxOUT4
33
12
TMDS_Data3-
RxOUT3
32
13
TMDS_Data3+
22
PLLGND RxOUT2
30
R133
24
PLLGND RxOUT1
29
DI 0 R 1 4
14
100
+5V_Power
RxOUT0
27
DI 0 R 1 3 1
15
SM_R_0603
GND(for +5V)
31
VCC
40
VCC RxCLKOUT
26
16
DI 0 R 1 3
Hot_Plug_Detect
48
VCC
56
IO13
DI 0 R 3 4
VCC
IO10
4
GND
28
GND
36
GND
17
TMDS_Data0-
44
GND
18
TMDS_Data0+
52
GND
19
DI 0 R 2 3
TMDS_Data0/5_Shield
20
TMDS_Data5-
21
TMDS_Data5+
22
TMDS_Clock_Shield
23
DNI 0 R 1 6 9
TMDS_Clock+
24
TMDS_Clock-
DNI 0 R 1 0
C1
DNI 0 R 1 7 3
Analog_Red
C2
Analog_Green
C3
DNI 0 R 1 6
Analog_Blue
C4
Analog_Horizontal_Sync
DNI 0 R 2 9
C5
DNI 0 R 2 5
Analog_Ground_1
C6
Analog_Ground_2
DVI_I
20
MDR Connector Supporting Circuits
DVDD
R64 DI 470
VCC33
LED will be OFF when
VCC33
a powered receiver is
TI_PVDD
B attached to DVI.
B
1
RXOUT7 R50 R50 0 DI CTL2
TI_TVDD
MDR_RX_IN0_N
DDC_Gnd_1
(MSEN low)
14
C13 C61 C56 C55
TxOut0-
2
C60 C59 C25 C26
MDR_RX_IN0_P
TxOut0Gnd
15
R123
D6
10uF 0_1uF 0_01uF 0_001uF
TxOut0+
3
10K
LED_Green
10uF 0_1uF 0_01uF 0_001uF
DI DI DI
DI
Sense
16
DI
DI DI DI DI
MDR_RX_IN1_N
USB/DDC_Gnd
4
DVDD R43 R43 10K DI BSEL
TxOut1-
17
MDR_RX_IN1_P
TxOut1Gnd
5
R46 R46 10K DI PDN
NS_LVCC
TxOut1+
18
3
DVDD
MDR_RX_IN2_N
DDC/SDA
6
R132 R132 10K DI PWRDWN
C9 C10 C52 C7
TxOut2-
19
Q3
C62 C58 C24 C12
MDR_RX_IN2_P
TxOut2Gnd
7
R32 R32 10K DI VREF
MSEN
BSS138LT1
10uF 0_1uF 0_01uF 0_001uF
TxOut2+
20
10uF 0_1uF 0_01uF 0_001uF
DI DI DI DI
USB+
8
R7 R7 10K DI DKEN
1 2
DI DI DI DI
USB_Shield
21
USB-
9
R47 R47 10K DI EDGE
MDR_RX_CLKOUT_N
DDC/SCL
22
NS_PVCC
TxClkOut-
10
NS_DVDD
MDR_RX_CLKOUT_P
TxClkOutGnd
R45 R45 10K DI ISEL
TOP Package View
23
C3 C64 C2 C1
TxClkOut+
11
C49 C57 C51 C50
USB_+5VDC
24
R44 R44 10K DI DSEL
(3) Drain
10uF 0_1uF 0_01uF 0_001uF
MDR_RX_IN3_N
DDC_+5VDC
12
10uF 0_1uF 0_01uF 0_001uF
DI DI DI DI
TxOut3-
25
R49 R49 0 DI CTL1
DI DI DI DI
MDR_RX_IN3_P
TxOut3Gnd
13
TxOut3+
26
R51 R51 0 DI CTL3
SOT-23
DDC_Gnd_26
R48 R48 10K DNI EDGE
27
(1) Gate (2) Source
Mounting_R
28
Mounting_L
J8 10226-1A10PE-ND
Channel Link - TX
A A
Title
Video Output
Size Document Number Rev
C MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 11 of 14
1
2
3
4
5

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 19. Audio In/Audio Out
1
2
3
4
5
PWM Analog Signal Output
Microphone
D D
VCC33
C69
0_1uF
DI
R147
2_2K
DI
VCC5
C70
U8
R154 0 DI AUDIO_SIG
TERM1
1
10uF
R145
TERM2
2
DI
330
CMA-4544PF-W
R146
100
DI DI
D2A_OUT
C C
R151
AUDIO_OUT
[14] AUDIO_OUT
2
Q4
C67
2N2369A
10uF
10K
DI
DI
R136
VCC33
DI 100
C68
J12
0_1uF
DI
DNI
2
Audio Amplifier
DI C47
3
0_1uF
1
Optional Bypass
AUDIO_SIG
PHONEJACK STEREO
VCC33
DI
C73 10uF R150 DI 10K R160 DI 680K
R161
0
R162
DNI
1000K
[14]
AUDIO_IN
4
DI
1
AUDIO_IN
B AUDIO_SIG
3
B
3
1
21
5 2
+
-
U13
MCP6L71R
R149
1000K
DI
A A
Title
AUDIO IN / AUDIO OUT
Size Document Number Rev
B MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 12 of 14
1
2
3
4
5

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 20. MachXO2 Supplies, JTAG
1
2
3
4
5
D D
MachXO2 JTAG Port
MachXO2 Power
Expand JTAG Chain to Prototype Header:
VCC33
J7
POWER
R155 0 DNI
TDI_HDR [7]
XO2_TDO
VCC_CORE
XO2_TDI
TDO_HDR [7]
XO2_TMS
XO2_TDO_PIN
XO2_TDO
VCCIO33
XO2_TCK
C C
XO2 JTAG HD
NOT Populated
C96
C88
0_1uF
0_1uF
DI
DNI
XO2_TMS
TMS_HDR [6,7,14]
XO2_TCK
TCK_HDR [6,7,14]
1
TDO 2
TDI
3
NC 4
TRST
5
TMS 6
GND 7
TCK 8
LCMXO2-1200-CSBGA132
U4E
R156
0
GND DNI
L2
GND G2
GND D2
GND B11
GND D13
GND H13
VCC P14
VCC A1
C7
NC
GND A5
VCC A14
GND L13
GND P10
GND P5
VCC N1
C5
VCCIO0
A8
C97 C76 C98
VCCIO0
B10
VCCIO0
0_1uF 0_1uF 0_1uF
L12
DI DI DI
VCCIO1
H14
R157
VCCIO1
D14
0 DI
VCCIO1
N11
VCCIO2
M6
VCCIO2
P1
VCCIO2
C92 C86
L1
VCCIO3
D3
0_1uF 0_1uF
VCCIO3
G1
DI DNI
VCCIO3
VCCIO33
VCCIO18
VCCIO33
22
XO2_TDI [6,14]
XO2_TMS [6,7,14]
XO2_TCK [6,7,14]
XO2_TDI
XO2_TMS
XO2_TCK
C94
0_1uF
XO2_TDO [6]
XO2_TDO
C103 C100
0_1uF 0_1uF
DI DI
C102
0_1uF
C101
0_1uF
C93
0_1uF
DNI
DNI
C77 C80
0_1uF 0_1uF
DI DI
C87
0_1uF
C95
0_1uF
DNI
DNI
DNI
DNI
C84 C90
0_1uF 0_1uF
DI DI
XO2_TDO_PIN [14]
XO2_TDO_PIN
B B
To Prototype Header
Expand JTAG Chain to Prototype Header:
R201
R202
JTAG Header
J12
TDO
R203
TDO
Socket (080SQ 132U6618A) Mounting Holes
MachXO2
MH2
MH16
MH13
TDI
TDI
MH1 MH1
1
M_HOLE1 M_HOLE1
DI
IW_MNT0 IW_MNT0
1
M_HOLE1
DI
IW_MNT0
1
M_HOLE1
DI
IW_MNT0
1
M_HOLE1
DI
IW_MNT0
A A
Title
XO2 Supplies, JTAG
Size Document Number Rev
B MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 13 of 14
1
2
3
4
5

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Figure 21. MachXO2 Top, Bottom
1
2
3
4
5
MachXO2 Bank 0
VCC18
XO2_IN3_2_P
0 R 3 0 DNI XO2_IO_0
[10] XO2_IN3_2_P
XO2_OUT3_P
XO2_OUT0_P
XO2_IN3_2_N
0 R 3 5 DNI XO2_IO_1
[11] XO2_OUT3_P
XO2_OUT3_N
XO2_OUT0_N
XO2_OUT0_P [11]
[10] XO2_IN3_2_N
[11] XO2_OUT3_N
XO2_OUT0_N [11]
LPDDR_A12
LPDDR_LDQS
D D
XO2_CLKIN_2_P
XO2_IO_2
XO2_CLKOUT_P
LPDDR_CKE_3p3
[8] LPDDR_A12
LPDDR_A11
XO2_GPIO_10
LPDDR_LDQS [8]
[10] XO2_CLKIN_2_P
[11] XO2_CLKOUT_P
XO2_CLKOUT_N
SW0
[8] LPDDR_A11
XO2_GPIO_10 [7]
XO2_CLKIN_2_N
XO2_IO_3
[11] XO2_CLKOUT_N
SW0 [7]
LPDDR_A9
LPDDR_DQ7
[10] XO2_CLKIN_2_N
XO2_OUT2_P
LPDDR_RASn
[8] LPDDR_A9
LPDDR_A8
LPDDR_DQ6
LPDDR_DQ7 [8]
XO2_IN2_2_P
XO2_IO_4
[11] XO2_OUT2_P
XO2_OUT2_N
LPDDR_BA0_3p3
LPDDR_RASn [8]
[8] LPDDR_A8
LPDDR_DQ6 [8]
[10] XO2_IN2_2_P
[11] XO2_OUT2_N
LPDDR_A7
LPDDR_DQ5
XO2_IN2_2_N
XO2_IO_5
XO2_OUT1_P
LPDDR_CASn
[8] LPDDR_A7
LPDDR_A6
LPDDR_DQ4
LPDDR_DQ5 [8]
[10] XO2_IN2_2_N
[11] XO2_OUT1_P
XO2_OUT1_N
LPDDR_CSn
LPDDR_CASn [8]
[8] LPDDR_A6
LPDDR_DQ4 [8]
XO2_IN1_2_P
0 R 5 7 DNI XO2_IO_6
[11] XO2_OUT1_N
LPDDR_CSn [8]
LPDDR_A5
LPDDR_DQ3
[10] XO2_IN1_2_P
SCL
LPDDR_BA1_3p3
[8] LPDDR_A5
LPDDR_A4
LPDDR_DQ1
LPDDR_DQ3 [8]
[4,7] SCL
XO2_IN1_2_N
XO2_IO_7
SDA
LPDDR_WEn
[8] LPDDR_A4
LPDDR_DQ1 [8]
[10] XO2_IN1_2_N
[4,7] SDA
LPDDR_WEn [8]
LPDDR_A3
LPDDR_DQ2
XO2_IN0_2_P
XO2_IO_8
XO2_TDO_PIN
SW1
[8] LPDDR_A3
LPDDR_A2
LPDDR_DQ0
LPDDR_DQ2 [8]
[10] XO2_IN0_2_P
[13] XO2_TDO_PIN
SW1 [7]
XO2_TDI
SW2
[8] LPDDR_A2
LPDDR_DQ0 [8]
[6,13] XO2_TDI
SW2 [7]
XO2_IN0_2_N
XO2_IO_9
LPDDR_CK
LPDDR_A0
[10] XO2_IN0_2_N
XO2_TCK
[8] LPDDR_CK
LPDDR_CKn
LPDDR_A1
LPDDR_A0 [8]
[6,7,13] XO2_TCK
XO2_GPIO_0
XO2_IO_0
XO2_TMS
[8] LPDDR_CKn
LPDDR_A1 [8]
[7] XO2_GPIO_0
[6,7,13] XO2_TMS
LPDDR_A10
XO2_GPIO_1
XO2_IO_1
[8] LPDDR_A10
[7] XO2_GPIO_1
LPDDR_LDM
[8] LPDDR_LDM
[7] XO2_GPIO_2
XO2_GPIO_2
XO2_IO_2
[7] XO2_GPIO_3
XO2_GPIO_3
0 R 1 4 1 DI XO2_IO_3
[7] XO2_GPIO_4
XO2_GPIO_4
XO2_IO_4
[7] XO2_GPIO_5
XO2_GPIO_5
XO2_IO_5
[7] XO2_GPIO_6
XO2_GPIO_6
XO2_IO_6
[7] XO2_GPIO_7
XO2_GPIO_7
XO2_IO_7
[7] XO2_GPIO_8
XO2_GPIO_8
XO2_IO_8
MachXO2 Bank 2
[7] XO2_GPIO_9
XO2_GPIO_9
XO2_IO_9
MachXO2 Bank 3
U4C
C C
XO2_IN3_1_P
Bank2
XO2_IO_2
[9] XO2_IN3_1_P
XO2_IN3_1_N
XO2_IO_3
[6] USB_UART_TX
USB_UART_TX
SW3
[9] XO2_IN3_1_N
SW3 [7]
[6] USB_UART_RX
USB_UART_RX
uSD_DAT2
XO2_SPI_CS0
XO2_IN0_1_P
uSD_DAT2 [8]
[8] XO2_SPI_CS0
[4] PM_SMBA_OUT3
PM_SMBA_OUT3
XO2_IN0_1_N
XO2_IN0_1_P [9]
uSD_CMD
PWM_FB_Delta_Sigma
XO2_IN0_1_N [9]
[8] uSD_CMD
uSD_CLK
uSD_DAT3
XO2_IN1_1_P
XO2_IO_4
[8] uSD_CLK
uSD_DAT3 [8]
[9] XO2_IN1_1_P
XO2_IN1_1_N
XO2_IO_5
uSD_DAT0
XIN
[9] XO2_IN1_1_N
[8] uSD_DAT0
X_2 [7]
[4,7] XO2_RESETn
XO2_RESETn
XOUT
X_1 [7]
XO2_SPI_CLK
XO2_IO_6
[7,8] XO2_SPI_CLK
MISO
XO2_IO_7
PM_MCLK
LVDS_COMP_P_VREF
[7,8] XO2_SPI_OUT
[4,7] PM_MCLK
uSD_DAT1
LVDS_COMP_N
PM_IN1
XO2_IO_8
[8] uSD_DAT1
[4] PM_IN1
PM_IN2
XO2_IO_9
AUDIO_OUT
[4] PM_IN2
[4] PM_OUT11
PM_OUT11
XO2_LED1
AUDIO_OUT [12]
XO2_LED1 [7]
XO2_CLKIN_1_P
XO2_IN2_1_P
[9] XO2_CLKIN_1_P
XO2_CLKIN_1_N
XO2_IN2_1_N
XO2_IN2_1_P [9]
[4] PM_OUT12
PM_OUT12
XO2_LED0
[9] XO2_CLKIN_1_N
XO2_IN2_1_N [9]
XO2_LED0 [7]
[4] PM_OUT13
PM_OUT13
XO2_LED2
XO2_LED2 [7]
XO2_IO_0
XO2_GPIO_11
XO2_GPIO_11 [7]
XO2_IO_1
PB20C/SN
MOSI
PM_PLDCLK
PB20D/SI/SISPI/IO0
P13
XO2_SPI_IN [7,8]
PM_PLDCLK [4,7]
XO2_LED3
XO2_LED3 [7]
N12
PB20A
PB20B
P12
M11
PB18D P11
PB18C M10
PB18B N10
PB18A M9
PB15D N9
PB15C P9
PB15B M8
PB11B/PCLKC2_1
PB15A
P8
N8
PB11A/PCLKT2_1 M7
U4B
B14
Bank1
0 R 3 3 DNI
PR2A
PR8A
J12
C13
PR2B
PR8B
J14
C14
PR2C
PR8C
D12
0 R 4 0 DNI
PR2D
E12
PR3A
E14
PR3B
E13
PR4A
F12
0 R 5 2 DNI
PR4B
F13
0 R 2 6 DNI
PR4C
F14
PR4D
G12
PR5A
G14
0 R 1 4 4 DI
PR5B
G13
PR5C/PCLKT1_0
H12
PR5D/PCLKC1_0
LCMXO2-1200-CSBGA132
0 R 1 3 9 DI
0 R 1 3 8 DI
0 R 1 5 3 DI
P2
PB4A
N2
PB4B
P3
PB4C/CSSPIN
M3
PB4D
N3
PB6A
P4
PB6B
M4
PB6C/MCLK/CCLK
N4
PB6D/SO/SPISO/IO1
N5
PB9C
M5
PB9D
N6
PB9A/PCLKT2_0
P6
PB9B/PCLKC2_0
P7
PB11C
N7
PB11D
J13
PR8D K12
PR9A
K13
PR9B
K14
PR9C L14
PR9D M13
PR10A M12
PR10B M14
PR10C N13
PR10D N14
U4A
A2
Bank0 Bank0
PT9A
PT15A
B3
PT9B
A3
PT10A
C4
PT10B
B5
PT11A
C6
PT11B
A7
PT12A/PCLKT0_1
B7
PT12B/PCLKC0_1
C8
PT12C/SCL/IO2/PCLKT0_0
B8
PT12D/SDA/IO3/PCLKC0_0
A4
TDO
B4
0 R 2 4 DNI
TDI
B6
TCK
A6
TMS
0 R 1 4 2 DI
LCMXO2-1200-CSBGA132
0 R 1 4 0 DI
C9
PT15B
A9
PT15C B9
PT15D/PROGRAMN C10
PT16A
A10
PT16B C11
PT16C A11
PT16D B12
PT17A C12
PT17B
A12
PT17C/INITN B13
1 0 K R 7 3 DI
0 R 2 8 DNI
PT17D/DONE
A13
0 R 1 4 3 DI
0 R 1 3 7 DI
0 R 1 5 2 DI
U4D
H1
Bank3 Bank3
PL5C
H3
PL5D
J1
PL8A
J2
PL8B
J3
PL8C
K2
PL8D
K1
PL9A/PCLKT3_0
K3
PL9B/PCLKC3_0
L3
PL10B
M1
PL10C
M2
PL10D
PL5B/PCLKC3_1 H2
PL5A/PCLKT3_1 G3
PL4D F3
PL4C F1
PL3D
PL4A
E3
PL4B
F2
E2
PL3C E1
PL3B/PCLKC3_2 D1
PL3A/PCLKT3_2 C2
PL2D/L_GPLLC_IN C3
PL2C/L_GPLLT_IN C1
0 R 4 2 DNI
PL2A/L_GPLLT_FB
B1
PL2B/L_GPLLC_FB
B2
MachXO2 Bank 1
Resistor Mux between Prototype Header
and Video Channel 2 (7:1LVDS)
23
LCMXO2-1200-CSBGA132
LCMXO2-1200-CSBGA132
B B
Interface between LVCMOS33 and LPDDR1.8V
ADC Delta-Sigma Interface
I2C Bus Pull-up Resistors
LVCMOS33 Open Drain LVCMOS33 Voltage Devider
LPDDR_BA1_3p3 LPDDR_BA0_3p3 LPDDR_CKE_3p3
VCC18
AUDIO_IN
VCCIO33
VCC33
820
DI R69
820
DI R188
J9
Jumper_2way DI
J9
Jumper_2way DI
1
2
3
AUDIO_IN R166 0 DI
ADC_IN R165 0 DI
820
DI R187
1K
DI R177
1K
DI R176
1K
DI R178
1K
DI R175
XO2_ADC_IN
4_7K
DI R90
LPDDR_BA1_1p8 LPDDR_BA0_1p8 LPDDR_CKE_1p8
[8] LPDDR_BA1 [8]
[8] LPDDR_CKE
LPDDR_BA0
R181
10K
R53
10K
DI
DI
4_7K
DI R91
IO12
LVDS_COMP_P_VREF
LPDDR_RASn
LPDDR_CASn
LVDS_COMP_N
SCL
SDA
1K
DI R74
1K
DI R183
1K
DI R182
R180
10K
R41
10K
DI
DI
LPDDR_CSn
LPDDR_WEn
C78
3300pF
DI
PWM_FB_Delta_Sigma
A A
Title
XO2 TOP, BOTTOM
Size Document Number Rev
C MachXO2 Control Board A
Date: Tuesday, February 15, 2011 Sheet 14 of 14
1
2
3
4
5

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Appendix B. Bill of Materials
Table 1. Bill of Materials
Item Quantity Reference Value PCB Footprint Mfr Part Number Manufacturer
1 19 C1, C7, C12, C14, C17, C26, C37, C39,
C50, C55, C71, C113, C114, C125, C131,
C132, C135, C137, C139
0_001uF SM_C_0201
2 23 C2, C5, C6, C15, C18, C24, C25, C32,
C34, C36, C38, C40, C41, C51, C52,
C56, C72, C91, C117, C124, C130, C136,
C138
0_01uF SM_C_0201
3 18 C3, C9, C13, C20, C21, C22, C43, C49,
C60, C62, C111, C118, C120, C121,
C122, C127, C129, C140
10uF SM_C_0603 C1608Y5V0J106Z TDK
4 2 C4, C11 12pF SM_C_0603
5 32 C8, C10, C16, C19, C42, C44, C45, C46,
C47, C57, C58, C59, C61, C63, C64,
C69, C74, C81, C89, C99, C105, C107,
C109, C110, C112, C115, C116, C123,
C128, C133, C134, C141
0_1uF SM_C_0603
6 2 C23, C29 18pF cc0402 C0402C180K3GACTU Kemet
7 3 C27, C30, C31 0.1uF cc0402 C0402C104K4RACTU Kemet
8 1 C28 10u cc0603 ECJ-1VB0J106M Panasonic
9 4 C33, C106, C142, C143 10uF SM_C_0805 JMK212BJ106KD-T TAIYO YUDEN
10 2 C35, C83 1uF SM_C_0805
11 7 C48, C82, C85, C104, C119, C126, C145 0.1uF cc0402 C0402C104K4RACTU Kemet
12 2 C53, C65 22uF SM_C_0805 LMK212BJ226MG-T TAIYO YUDEN
13 4 C54, C66, C70, C73 10uF SM_C_0805
14 1 C67 10uF SM_C_0603
15 1 C68 0_1uF SM_C_0603
16 13 C75, C76, C77, C79, C80, C84, C90,
C92, C96, C97, C98, C100, C103
0_1uF SM_C_0201
17 1 C78 3300pF SM_C_0603
18 8 C86, C87, C88, C93, C94, C95, C101,
C102
0_1uF SM_C_0201
19 1 C108 0_01uF SM_C_0201 EMK107BJ103K TAIYO YUDEN
20 1 C144 4u7 cc0603 ECJ-1VB0J475K
21 8 D1, D2, D3, D4, D7, D8, D9, D10 LED SM_D_0603 LTST-C190CKT LITE ON
22 2 D5, D6 LED_Green SM_D_0603 LTST-C190KGKT LITE ON
22a 1 D11 LED_Green SM_D_0603 LTST-C190KGKT LITE ON
23 1 D12 LED SM_D_0603 LTST-C190CKT LITE ON
24 15 IO2, IO3, IO4, IO5, IO9, IO10, IO11, IO12,
IO13, IO14, IO16, IO17, IO18, IO19, IO20
T POINT R TP
25 3 IO7, IO8, IO15 T POINT R TP
26 2 J1, J8 10226-1A10PE-ND 10226-1A10PE-ND 10226-1A10PE 3M
26a 1 J13 10226-1A10PE-ND 10226-1A10PE-ND 10226-1A10PE 3M
27 2 J2, J3 DVI_I DVI_I 74320-1004 Molex
27a 1 J10 DVI_I DVI_I 74320-1004 Molex
28 1 J4 CON40A 2x20x100mil TSW-120-07-G-D Samtec
29 1 J5 USB_MINI_B TYPE_B UX60-MB-5ST Hirose
30 1 J6 Jumper_2way JP_2WY TSW-103-07-G-S Samtec Inc.
30 1 J9 Jumper_2way JP_2WY TSW-103-07-G-S Samtec Inc.
31 1 J7 XO2 JTAG HD XO2_JTAG_HD
32 1 J11 PWR_JACK PWR_CON RAPC712 Switchcraft
33 1 J12 PHONEJACK
STEREO
SM MJ1-3510-SMT CUI
34 1 L3 600ohm 500mA FB0603 BLM18AG601SN1D Murata
35 4 MH1, MH2, MH13, MH16 M_HOLE1 IW_MNT0 SJ-5003 (BLACK)
36 4 Q1, Q3, Q6, Q8 BSS138LT1 SOT_23 BSS138LT3G ON Semi
37 2 Q2, Q5 2N7002E SM_SOT23 2N7002ET1G ON_Semi
24

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Table 1. Bill of Materials (Continued)
Item Quantity Reference Value PCB Footprint Mfr Part Number Manufacturer
38 1 Q4 2N2369A 2N2369A_SOT23 MMBT2369A Fairchild
39 1 Q7 ZDT758 SM_8_DUAL_PNP ZDT758 Diodes/Zetex
40 2 RN1, RN4 RN2_4_470 RN2_4_470_0603 TC164-JR-07470RL Yageo
41 1 RN2 RN1_8_10K RN1_8_10K_0603 MNR18E0APJ103 Rohm Semi
42 1 RN3 RN1_8_10K RN1_8_10K_0603 MNR18E0APJ103 Rohm Semi
43 45 R1, R7, R18, R19, R20, R21, R32, R41,
R43, R44, R45, R46, R47, R53, R73,
R81, R94, R97, R115, R116, R117, R118,
R119, R120, R121, R123, R124, R125,
R126, R127, R128, R132, R151, R158,
R159, R163, R164, R180, R181, R200,
R233, R236, R239, R242, R244
10K SM_R_0402
44 1 R2 1M SM_R_0603
45 48 R3, R5, R8, R10, R11, R15, R16, R24,
R25, R26, R28, R29, R30, R33, R35,
R40, R42, R52, R57, R92, R96, R98,
R100, R104, R105, R106, R109, R110,
R113, R155, R156, R161, R168, R169,
R172, R173, R207, R208, R209, R210,
R211, R212, R213, R214, R215, R216,
R217, R218
0 SM_R_0402
46 5 R4, R67, R195, R196, R232 1K SM_R_0603
47 68 R6, R9, R12, R13, R14, R17, R23, R34,
R36, R37, R38, R39, R49, R50, R51,
R61, R62, R70, R71, R75, R76, R78,
R82, R83, R87, R93, R95, R99, R102,
R103, R107, R108, R111, R112, R131,
R137, R138, R139, R140, R141, R142,
R143, R144, R152, R153, R154, R157,
R165, R166, R167, R170, R171, R174,
R186, R220, R221, R222, R223, R224,
R225, R226, R227, R228, R229, R230,
R231, R247, R248
0 SM_R_0402
48 7 R22, R48, R101, R237, R243, R245,
R246
10K SM_R_0402
49 4 R27, R64, R114, R122 470 SM_R_0603 ERJ-3EKF4700V Panasonic
ECG
50 1 R31 510, 1% SM_R_0603
51 9 R54, R55, R65, R66, R84, R85, R88,
R89, R205
4_7K SM_R_0603
52 1 R56 2k2 cr0402 TNPW04022K20BEED Vishay/Dale
53 1 R58 0 SM_R_0805
54 1 R59 1 SM_R_0805
55 2 R60, R219 220 SM_R_0603
56 2 R63, R68 0 SM_R_0603
57 3 R69, R187, R188 820 SM_R_0402
58 8 R74, R175, R176, R177, R178, R182,
R183, R240
1K SM_R_0402
59 1 R79 100K SM_R_0603
60 2 R80, R86 68 SM_R_0402
61 2 R90, R91 4_7K SM_R_0402
62 5 R129, R130, R133, R134, R135 100 SM_R_0603
63 8 R136, R146, R184, R185, R191, R194,
R201, R206
100 SM_R_0603
64 1 R145 330 SM_R_0603
65 1 R147 2_2K SM_R_0603
66 2 R148, R235 2 SM_R_0805
67 2 R149, R162 1000K SM_R_0603
68 1 R150 10K SM_R_0603
69 1 R160 680K SM_R_0603
70 2 R179, R198 200 SM_R_0603
71 4 R189, R190, R192, R193 3_92K SM_R_0603
72 2 R197, R204 2K SM_R_0603
25

MachXO2 Control Development Kit
Lattice Semiconductor User’s Guide
Table 1. Bill of Materials (Continued)
Item Quantity Reference Value PCB Footprint Mfr Part Number Manufacturer
73 1 R199 12k cr0402 RC0402FR-0712KL Yageo
74 4 R202, R203, R241, R249 10k cr0402 RC0402FR-0710KL Yageo
75 0 R240 2k2 cr0402 RC0402FR-072K2L Yageo
76 1 SW1 SWDIP_4 SMD_8check 3-5435640-5 Tyco
77 1 SW2 SW DIP_2 SP_75 195-2MST CTS
78 1 S1 XO2 Global Reset SMT_SW EVQ-Q2K03W Panasonic
79 1 U1 microSD Socket SM_SD 460DE08C3 MULTICOMP
80 1 U2 TFP401A HTQFP_100 TFP401APZPG4 TI
80 1 U9 TFP401A HTQFP_100 TFP401APZPG4 TI
81 1 U3 TFP410 HTQFP_64 TFP410PAP TI
82 1 U4 LCMXO2-1200- CSBGA132 LCMXO2-1200- Lattice Semi
CSBGA132
CSBGA132
83 1 U5 STG3693QTR QFN STG3693QTR STMicroelectronics
84 1 U6 MT46H16M16LFBF SM/60VFBGA MT46H16M16LFBF Micron
85 1 U7 ispPAC-POWR1014A TQFP_48 ispPAC-POWR1014A-
01TN48I
Lattice
86 1 U8 CMA-4544PF-W 2 Solder Pins (TH) CMA-4544PF-W CUI Inc
87 1 U10 DS90CR288A TSSOP_56 DS90CR288AMTD/NOP National
B
Semi
88 1 U11 NCP1117ST33 SOT_223 NCP1117ST33T3G ONSemi
89 1 U12 NCP1117ST18 SOT_223 NCP1117ST18T3G ONSemi
90 1 U13 MCP6L71R SOT_23_5_MC MCP6L71RT-E/OT Microchip
91 1 U14 AT25DF041A-SH-B SOIC8 AT25DF041A-SH-B Atmel
92 1 U15 AT25DF041A-MH-B UDFN AT25DF041A-MH-B Atmel
93 1 U16 AD8604ARZ 14_SOIC AD8604ARZ Analog
Devices
95 1 U17 Value MRA08A_M LP3879MR-1.2 National
96 1 U18 DS90CR287 TSSOP_56 DS90CR287MTD/NOPB TI
96 1 U19 DS90CR287 TSSOP_56 DS90CR287MTD/NOPB TI
97 1 U20 FT2232HL tqfp64_0p5_12p2x12
p2_h1p6
FT2232HL FTDI
98 1 U21 93LC56-SO8 so8_50_244 93LC56T-I/SN Microchip
99 1 X1 CTS-CB3LV-3C-25MHz SMD 7.00mm x
5.00mm
CB3LV-3C-25M0000 CTS
100 1 X2 HCM49 24.000MABJ-UT SMD HCM49 24.000MABJ-UT Citizen Finetech
101 1 X3 12MHZ crystal_4p_3p2x2p5 7M-12.000MAAJ-T TXC CORP
102 1 XO2_Control_board_RevE_PCB 305-PD-11-XXX
26