Presentation - Analysis of High-speed Differential Line on PCB ...

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Presentation - Analysis of High-speed Differential Line on PCB ...

ong>Analysisong> ong>ofong> ong>Highong>-ong>speedong> ong>Highong> ong>speedong> ong>Differentialong> ong>Lineong> on PCB using HFSS

2002. 10. 1

Terahertz Interconnection and Package Laboratory

KAIST (Korea Advanced Institute ong>ofong> Science and Technology)

Seungyong Baek (? ??)

Homepage : http://tera.kaist.ac.kr


Research Fields at TERA Lab. (in the view ong>ofong> Motherboard)

Twisted Pair on PCB/Chip

Modular Jack

EMI

Signal line across Split plane design

Spread Spectrum Clock Driver

Connector Modeling

Power Plane Design

Mixed Mode Power Plane Modeling

Split Power System Modeling

MESH Plane Modeling

Via Modeling

Crosstalk Modeling

Single ong>Lineong> Modeling

ESD

Embedded Passive Modeling

SMT Component Modeling

SATA

ong>Differentialong> ong>Lineong> Modeling

BGA Modeling

Adaptive Output Driver

2/31

Meander LINE

Memory Module Design

RAMBUS

WLP


Contents

� Introduction ong>ofong> ong>Differentialong> Signaling Scheme

� Characterization ong>ofong> ong>Differentialong> Signaling Scheme by Fabrication Error

� Impedance Change by Edge-Placement ong>ofong> ong>Highong>-ong>speedong> ong>Differentialong> ong>Lineong>s

� An Evaluation ong>ofong> ong>Differentialong> Impedance in PCBs Using Two Single-

Ended Probes Only

� Conclusion

3/31


Introduction – Frequency Increase

Frequency [GHz]

7

6

5

4

3

2

On-chip Local Clock

(ong>Highong>-performance)

1

Chip-to-Board

(ong>ofong>f-chip) Speed (high-performance, for peripheral buses)

0

2000 2002 2004 2006 2008

Year

2010 2012 2014

Ref.) ITRS (International Technology Roadmap for Semiconductors), 2000, SIA

� Off-chip data rate should move to the range ong>ofong> Gb/s-per-pin

? increased complexity and cost due to massive parallelism

4/31


Introduction – Power Supply Voltage Decrease

Power Supply Voltage [V]

2.1

1.8

1.5

1.2

0.9

0.6

0.3

Minimum logic V dd (V)

for minimum power

Minimum logic V dd (V)

for maximum performance

0

2000 2002 2004 2006 2008 2010 2012 2014

Year

Ref.) ITRS (International Technology Roadmap for Semiconductors), 2000, SIA

� Reduction ong>ofong> power supply voltage

? power dissipation, transistor channel length, reliability ong>ofong> gate dielectric

5/31


Why ong>Differentialong> Signaling?

� Reduction ong>ofong> Crosstalk between Circuits

� Reduction ong>ofong> Simultaneous Switching Noise (SSN)

� Reduction ong>ofong> EMI

� Minimization ong>ofong> Common-mode noise

� Design ong>ofong> Low-voltage, Low-power

ong>Highong>-ong>speedong> digital circuit

6/31


Objective

� Using HFSS simulation and Testing,

� A Characterization ong>ofong> ong>Differentialong> Signaling Scheme by Fabrication Error

� A Demonstration ong>ofong> Impedance Change by Edge-Placement ong>ofong> ong>Highong>-ong>speedong>

ong>Differentialong> ong>Lineong>s

� An Evaluation ong>ofong> New Test Method ong>ofong> ong>Differentialong> ong>Lineong>s Using Two Single-

Ended Probes Only

7/31


Process Variation Problem in ong>Differentialong> ong>Lineong> Scheme

Seungyoung Ahn, Albert Chee W. Lu, Wei fan, lai L Wai, and Joungho Kim, “Solution Space ong>Analysisong> ong>ofong> Interconnects

for Low Voltage ong>Differentialong> Signaling ( LVDS) Applications”, IEEE 10th Topical Meeting on Electrical Performance ong>ofong>

Electronic Packaging (EPEP2001), pp. 297-330, Boston, USA, Oct. 2001.

? w

? s

ong>Differentialong>-Mode

� Variation ong>ofong> fabrication error : (? w, ? s) > (? h)

Common-Mode

� Variation ong>ofong> fabrication error ? field change ? variation ong>ofong> electrical characteristics

� Variation ong>ofong> electrical characteristics by fabrication error

ong>Differentialong>-mode > Common-mode

? h

8/31


Device Under Test

DUT Width Space Width ? ?

#1

#2

#3

#4

#5

100 µm 125 µm –20 %

112.5 µm

125 µm

137.5 µm

150 µm

125 µm

125 µm

125 µm

125 µm

–10 %

0 %

10 %

20 %

� ??? ? 10%? ?? ??? ???.

???

� ?? ??? ??? ???? ???? ??

DUT Width Space Space ? ?

#6

125 µm

125 µm

125 µm

125 µm

125 µm

100 µm –20 %

112.5 µm

125 µm

137.5 µm

150 µm

???? ???? Signal line? Width? Space? ±10%, ±20% ? ?.

#7

#8

#9

#10

9/31

–10 %

0 %

10 %

20 %


Characteristic Parameters – 1.Characteristic Impedance (Z 0 )

Voltage (V)

±20% ong>ofong> Width variation for ong>Differentialong>-mode signaling

Circuit Simulation (? ? TDR Setup) Full-wave simulation

4.9 % reflection

Time (ns)

� Z ong>Differentialong>-mode (100 Ohm) ˜ Z Cable (50×2 = 100 Ohm) ? ? Matching.

� Width? (20%) � Reflection ? ? (4.9 %)

1 + Γref

1 + Γ

ΔZ

= Z ref − Z = 100 × −100

× ? ??, Z0 ? (10.3 %)

1 − Γref

1 − Γ

� 4.9% reflection � 10.9% Z0 ?? (full-wave Simulation),

Z 0 (Ohm)

140

120

100

80

10.9 %

100 125 150

Width (µm)

10/31


Characteristic Parameters – 1.Characteristic Impedance (Z 0 )

±20% ong>ofong> Width variation for Common-mode signaling

Circuit Simulation (? ? TDR Setup) Full-wave simulation

Voltage (V)

4.8 % reflection

Time (ns)

� Z Common-mode (33Ohm) > Z Cable (50/2=25Ohm)? ? ?? Mismatching

� Width? (20%) � Reflection ? ? (4.8 %)

� 4.8% reflection � 10.9 % Z 0 ?? (full-wave Simulation)

Z 0 (Ohm)

70

50

30

10

10.9 %

100 125 150

Width (µm)

11/31


Characteristic Parameters – 1.Characteristic Impedance (Z 0 )

±20% ong>ofong> Space variation for ong>Differentialong>-mode signaling

Circuit Simulation (? ? TDR Setup) Full-wave simulation

Voltage (V)

1.8 % reflection

Time (ns)

� Z ong>Differentialong>-mode (100 Ohm) ˜ Z Cable (50×2 = 100 Ohm) ? ? Matching.

� Space? (20%) � Reflection ? ? (1.8 %)

Z 0 (Ohm)

� 1.8% reflection � 3.2% Z 0 ?? (full-wave Simulation)

140

120

100

80

3.2 %

100 125 150

Space (µm)

12/31


Characteristic Parameters – 1.Characteristic Impedance (Z 0 )

Voltage (V)

±20% ong>ofong> Space variation for Common-mode Signaling

Circuit Simulation (? ? TDR Setup) Full-wave simulation

1.1 % reflection

Time (ns)

Z 0 (Ohm)

70

50

30

10

2.6 %

100 125 150

Space (µm)

� Z Common-mode (33 Ohm) > Z Cable (50/2=25 Ohm) ? ? ?? Mismatching

� Space? (20%) � Reflection ? ? (1.1 %)

� 1.1% reflection � 2.6% Z 0 ?? (full-wave Simulation)

13/31


Effect by Edge Placement ong>ofong> ong>Differentialong> ong>Lineong>

Seungyong Baek, Derek Kam, Bongcheol Park, Jung-Gun Byun, Cheol-Seung Choi, and Joungho Kim, “Increased Radiated

Emission and Impedance Change by Edge-Placement ong>ofong> ong>Highong>-ong>speedong> ong>Differentialong> ong>Lineong>s on Printed Circuit Board,” 2002

IEEE International Symposium on Electromagnetic Compatibility, vol 1, pp 200-204, Minnesota USA.

? Consider the effects by edge placement ong>ofong> high-ong>speedong> differential lines

? Demonstrate differential mode impedance change by edge placement

? Certificate variation ong>ofong> radiated emission using simulation and measurement

ong>Lineong> Width = 0.4mm

Pitch=0.7mm

Substrate Width=20mm

Distance to edge (D)

Height = 0.3mm

Substrate

length=80mm

Test PCB with finite width ground

14/31

10mm

0.8mm


Current density ong>ofong> differential pair (Simulation)

Substrate

Air

Trace 1 Trace 2 Trace 1 Trace 2

Substrate

(a) (b)

Air

10mm 1mm

Current density when the distance to edge is 10mm Current density when the distance to edge is 1mm

� When differential pair is located in the center ong>ofong> PCB, current density is balanced in case ong>ofong> (a)

� The balance ong>ofong> current density is broken by edge placement in case ong>ofong> (b)

15/31


ong>Differentialong> impedance change by edge placement (Simulation)

Impedance [ohm]

110

100

90

80

70

60

50

40

30

65

60

55

50

45

40

35

30

ong>Differentialong> mode impedance

25

1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6

Common mode impedance

20

10 9 8 7 6 5 4 3 2 1 0

Distance to edge (D) [mm]

ong>Differentialong> mode impedance remains about 100Ω from 10mm to 2mm

ong>Differentialong> mode impedance suddenly falls ong>ofong>f when D is 1mm

16/31


Measurement setup ong>ofong> differential impedance

ong>Differentialong> TDR module 80E04 + Sampling Oscilloscape TDS 8000B

( Reflected rising time= 30ps )

Test PCB

50Ω termination

Test setup for measuring the differential mode impedance

17/31


Measurement results – differential mode impedance

ong>Differentialong> Impedance [ohm]

120

110

100

90

80

70

60

Distance to the edge (D) = 10mm

Reduction ong>ofong> 17%

Distance to the edge (D) = 0.8mm

44.4 44.6 44.8 45 45.2 45.4 45.6 45.8 46 46.2

Time [ns]

� Distance to the edge = 10mm � ong>Differentialong> mode impedance = 102Ω

� Distance to the edge = 0.8mm � ong>Differentialong> mode impedance = 85Ω

� The differential mode impedance suddenly falls ong>ofong>f to 85Ω when D = 0.8mm

18/31


Variation ong>ofong> radiated emission by edge placement

Edge placement ong>ofong> high-ong>speedong> differential lines

Balance ong>ofong> the differential lines is collapsed

Balance ong>ofong> the current density is also broken

Increase ong>ofong> common mode current

Variation ong>ofong> radiated emission

19/31


Radiated emission according to location ong>ofong> differential pair

150

210

Total electric field plot at 1GHz (V/m)

120

240

90

0.2

0.6

0.4

60

30

180 0

270

300

D=10mm (a)

D=3mm (b)

D=1mm (c)

D=0.8mm (d)

330

Simulated total electric field at 1GHz

MAX : 0.25V/m

MAX : 0.522V/m

(a)

(b)

(c)

(d)

20/31

10mm

3mm

1mm

0.8mm


Measurement setup ong>ofong> radiation emission

DC

Power

Supply

100MHz

Crystal

Oscillator

Spectrum Analyzer

180°

Phase Shifter

Shielding Box

180°


Antenna

Anechoic Chamber

Radiated Emission

Test PCB

Test setup for measuring an amount ong>ofong> the radiated emission

21/31


Measurement result – maximum radiated emission

dBm

-55

-60

-65

-70

-75

-80

Maximum Spectrum (Peak-to-Peak envelop)

D=10mm

D=7mm

D=5mm

D=3mm

-85

100 200 300 400 500 600 700 800 900 1000

Frequency [MHz]

? The closer differential pair to the PCB edge, the more radiated emission occur

? When the differential pair is placed at the edge ong>ofong> the PCB, the shielding effect

by the ground plane is no longer effective

22/31


Conventional Method 1: ong>Differentialong> TDR

Dong Gun Kam, Heeseok Lee, Woonghwan Ryu, Jonghoon Kim, Bongcheol Park, and Joungho Kim, "An Evaluation ong>ofong>

ong>Differentialong> Impedance in PCBs Using Two Single-Ended Probes Only," IEEE Workshop on Signal Propagation on

Interconnects (SPI), 2002

S. Corey, et al., “Electronic Package Characterization Using ong>Differentialong> TDR Techniques”,

Proc. IEEE 9 th Topical Meeting on Electrical Performance ong>ofong> Electronic Packaging, 2000, pp. 172-174.

� Only a small skew ong>ofong> TDR pulses can result in considerable error.

B. J. Rubin, “Understanding Modeling and Measurements ong>ofong> ong>Differentialong> Transmission ong>Lineong>s”,

Proc. IEEE 10 th Topical Meeting on Electrical Performance ong>ofong> Electronic Packaging, 2001, pp. 313-316

� Its instrumentation is expensive because ong>ofong> such difficulties as

synchronizing two TDR pulses.

23/31


Conventional Method 2: Balun

2-port VNA

Balun DUT

Balun

� Balun = Power Splitter + Phase Shifter

� It is very difficult to make broadband baluns.

24/31


Conventional Method 3: Mixed-Mode Mixed Mode S-parameters

S parameters

D. E. Bockelman, “Combined ong>Differentialong> and Common-Mode Scattering Parameters: Theory and

Simulation”, IEEE Trans-MTT, Vol. 43, No. 7 (1995), pp. 1530-1539

� Although it is theoretically perfect, it is very expensive.

25/31


What’s What s the Matters with the Conventional Methods

Balun

Only narrow-band

Need for

de-embedding balun effect

4-port Measurement

Expensive

ong>Differentialong> TDR

Accurate synchronization ong>ofong>

two TDR pulses is required

Expensive

26/31


Proposed Method

� Two single-ended probes are connected to each signal traces

with a metallic plane on the bottom layer floating.

27/31


Measured Results

� Device-Under-Test (DUT) : Coupled Microstrip ong>Lineong>

DUT

#1

#2

#3

W

(width)

3mm

2mm

1mm

� Measured ong>Differentialong> Impedance at 500MHz

DUT

#1

#2

#3

Proposed

Method

67.1O (-1.0%)

86.7O (-2.1%)

126O (-2.3%)

4-port

Measurement

67.8O

88.6O

129O

S

(space)

2mm

3mm

4mm

H

(dielectric)

28/31

1mm

1mm

1mm

Simulation

(MoM)

68.9O (+1.1%)

91.1O (+2.8%)

132O (+2.3%)


Full Wave Simulation (Using Ansong>ofong>t HFSS)

DUT

#1

#2

#3

500 MHz

72.9O (+7.5%)

91.4O (+3.2%)

126.8O (-1.7%)

2 GHz

72.3O (+6.6%)

91.3O (+3.0%)

126.5O (-1.9%)

5 GHz

73.2O (+8.0%)

91.0O (+2.7%)

126.8O (-1.7%)

29/31

Ref.

67.8O

88.6O

129 O


The PROS and CONS ong>ofong> the Proposed Method

Disadvantage

Advantage

ong>Differentialong> only

Simple

Cheap

Non-invasive

Practical !!!

30/31


Conclusion

? We have been researching Signal Integrity, Power/Ground Integrity

and EMI in Tera Lab.

? We introduced ong>Differentialong> Signaling Scheme

� Variation ong>ofong> differential line characteristics by fabrication error

� Change ong>ofong> differential impedance by edge placement

� Proposal ong>ofong> new test method ong>ofong> differential lines

31/31

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