(Ignored by HDL Compiler) 1.

testlab.ncue.edu.tw

(Ignored by HDL Compiler) 1.

Hardware Description Language

-- Logic Design using Verilog

Tsung-Chu Huang

Dept. of Electronic Eng.

National Changhua University of Ed.

Email: tch@cc.ncue.edu.tw

2004/10/19

HDL T.-C. Huang / NCUE Fall 2004 1


Directives in Verilog

`back-quote and $dollar-sign Directives

� Preprocessor

1. Macro Substitutions: `define sym string

2. Include Construct: `include file

3. Conditional Process: `ifdef sym `endif

� Simulation Directives: (Ignored by HDL Compiler)

1. `timescale unit / precision

2. `resetall

� System Functions: (Prefixed by $)

1. $display, $write: write a message to the display

2. $monitor: monitoring every event

3. $time: return the circuit simulation time

4. $stop, $continue

5. $finish

HDL T.-C. Huang / NCUE Fall 2004 2


Example

`include ”parts.v”

`timescale 1ns/1ps

`define high 7:4

`define Sum {C, S}

module xyz(input, output);

:

parameter five = 4’b0101;

:

Assign `Sum = Bus[`high] + five;

:

Endmodule

module testbench;

initial begin

:

$monitor($time, ”Sum=%b, Adr=%H”, Sum, A);

:

#10 $stop;

end

endmodule

HDL T.-C. Huang / NCUE Fall 2004 3


� Compilation Directives

Function and Task

1. The same as function/procedure in PASCAL

2. and non-void/void functions in C.

� Advantage:

1. Fast, convenient and easy to maintain the source code.

2. Convenient for reading.

3. Repetition and duplication

HDL T.-C. Huang / NCUE Fall 2004 5


Example of Function

module xyz(Clk, X, Y);

:

always(posedge Clk)

begin :X


z

Switch-Case

case, casex, casez

case (expression)

constant1: statement1;

:

constantj: statementj;

:

default: statementd;

endcase

x

0, 1

?

casex(c)

4’b00xx: statement1;

:

4’b0xxx: statementj;

:

default: statementd;

endcase

casez(c)

8’b01z?11??: statement1;

:

8’b1100????: statementj;

:

default: statementd;

endcase

HDL T.-C. Huang / NCUE Fall 2004 8


Huffman Model for a Finite State Machine

Single Clock, Synchronous, DFF-based

PI:

Primary Inputs

PPI:

Pseudo PI

X Z

L

Clk

M

PS: Present State

Combinational

Circuit

Q

y

Q D

Q D

Q D

Q D

PO:

Primary Outputs

PPO:

Pseudo PO

HDL T.-C. Huang / NCUE Fall 2004 9

D

M

N

Y NS: Next State

State Count S ≤ 2

M


Classification of FSM’s

� Mealy Machine: The

outputs are dependent

on both the state and

the input.

� Moore Machine: The

outputs are dependent

on only the present state.

Combinational

Circuit

HDL T.-C. Huang / NCUE Fall 2004 10


State Diagram

Example of Mealy Machine: A Lock with Password 1101

0/0

Waiting for

1011

1/0

Waiting for

011

00 01

1/1

Waiting for

11

HDL T.-C. Huang / NCUE Fall 2004 11

0/0

Waiting for 0/0

1 1/0

0/0

11 10

1/0


Q 1

0

0

0

0

1

1

1

1

Q

Q 0

1

0

0

1

1

State Table & Flow Table

Transition Table

0

0

1

X

X 0

0

1

0

1

0

1

0

1

D 1

0

0

1

0

0

1

1

0

D

D 0

0

1

0

1

0

1

0

1

Z

Z 0

0

0

0

0

0

0

0

1

K-map or

McKlusky Method:

D1 = Q1X

+ Q1Q0

X + Q1Q0

X

D =

0

HDL T.-C. Huang / NCUE Fall 2004 12

X

Z = Q1Q0

X

X

Q0D Q1D Z


Typical Verilog Description

Example of Mealy Machine: A Lock with Password 1101

module Lock(Clk, X, Z)

input Clk, X;

output Z;

reg Z;

parameter W1011=2’b00, W011=2’b01, W11=2’b10, W1=2’b11;

reg [1:0] Present_State, Next_State;

always@(posedge Clk)

Present_State = Next_State;

always@(X or Present_State) begin

Next_State = Present_State;

case(Present_State)

W1011 : Next_State = X ? W011 : W1011;

W011 : Next_State = X ? W011 : W11;

W11 : Next_State = X ? W1 : W1011;

W1 : Next_State = X ? W011 : W11;

default: Next_State = W011;

endcase

case(Present_State)

W1 : Z = X ? 1 : 0;

default: Z = 0;

endcase

end // always

endmodule

HDL T.-C. Huang / NCUE Fall 2004 13


State Diagram

Example of Moore Machine: Recent Ones

0

1

S0

0

S3

2

1

HDL T.-C. Huang / NCUE Fall 2004 14

0

1

0

S1

1

1

S2

1

0


State Diagram

Example of Moore Machine: Recent Ones

HDL T.-C. Huang / NCUE Fall 2004 15


Typical Verilog Description

Example of Mealy Machine: A Lock with Password 1101

module Recent1s(Clk, X, Z)

input Clk, X;

output [1:0] Z;

reg [1:0] Z;

reg [1:0] Present_State, Next_State;

always@(posedge Clk)

Present_State = Next_State;

always@(X or Present_State) begin

Next_State = Present_State;

case(Present_State)

0 : Next_State = X ? 1 : 0;

1 : Next_State = X ? 2 : 1;

2 : Next_State = X ? 1 : 0;

3 : Next_State = X ? 2 : 1;

default: Next_State = 0;

endcase

end // always

assign Z = Present_State[1] + Present_State[0];

endmodule

Moore decoder from present state to output

HDL T.-C. Huang / NCUE Fall 2004 16


JTAG, IEEE1149.1 and Boundary Scan

� Reason to Introduce this Example

� JTAG

1. JTAG is often used in the FPGA flow for HDL practice

2. It is a good example for FSM

3. a common knowledge for seniors in electronic eng.

1. JTAG (Joint Test Action Group)

2. IEEE 1149.1 – compatible boundary scan access port for

printed circuit board-level continuity and diagnostic testing of the

device in which all digital input, output, and input/output pins are

tested.

HDL T.-C. Huang / NCUE Fall 2004 17


Hierarchical Board-level Test and

Transmission

Pull them up to test?

HDL T.-C. Huang / NCUE Fall 2004 18


TDI

Boundary Scan

Basic Concept

TDO

HDL T.-C. Huang / NCUE Fall 2004 19


Boundary Scan

Background

1. Joint Test Action Group (JTAG) Boundary Scan

Standard, 1988

2. IEEE P1149.1 Testability Bus Standard (Proposal), 1989

3. Basic Structure:

• TAP (Test Access Port) Controller

• Registers: IR (Instruction Register) and BR

(Bypass Register)

• Extra Pins:

� TMS (Test Mode Singal)

� TCK (Test Clock)

� TDI (Test Data Input)

� TDO (Test Data Output)

HDL T.-C. Huang / NCUE Fall 2004 20


TDI

TMS

Boundary Scan

Chip Architecture for BS1149.1

TAPC

TCK

Application Circuit

probably with scan chains

IR

TDO

HDL T.-C. Huang / NCUE Fall 2004 21

BR


A Basic Boundary Scan Cell

IN

0

1

SCAN_IN Shift

1

Clock

0

SCAN_OUT

Update mode

D Q D Q

Update

Capture mode

Scan mode

HDL T.-C. Huang / NCUE Fall 2004 22

0

1

Mode

1 0

Normal mode

OUT

• Can update PIs (capture POs) simultaneously

for detecting delay response.

• Can be used both as input and output boundary

scan cells.


Basic Test Access Controller

A Synchronous Finite State Machine with 2X8 States

1

0

TestReset

0

Start/Iddle

11111

11

1

Meta-state for

Instruction Operations

Meta-state for

Data Operations

HDL T.-C. Huang / NCUE Fall 2004 23


1

0

TestReset

0

Start/Iddle 1

State Diagram of TAPC

0

SelectDR

0

CaptureDR

0

ShiftDR

1

Exit1DR

0

PauseDR

1

Exit2DR

1

SelectIR

0

CaptureIR

ShiftIR

Exit1IR

PauseIR

Exit2IR

UpdateDR

UpdateIR

1 0 1 0

HDL T.-C. Huang / NCUE Fall 2004 24

1

1

0

0

1

0

0

1

0

1

1

1

1

0

0

1


Boundary Scan

Exercise with TI BS1.0

1. Exercise and trace some examples using TI Scan

Educator 1.0 (downloaded from TI or my web).

2. Write the basic TMS sequence for applying a pattern

and detecting the result to a circuit under test (CUT)

originally with 4 pins.

Hint: Initialization, Scanning in 4 bits, Update, Capture,

Scanning out 4 bits, Update.

3. Homework #2: Design a Boundary Scan Control

according to the above state diagram using Verilog

(due in 2 Weeks)

4. You can trace it by comparing to TI Scan Educator 1.0

HDL T.-C. Huang / NCUE Fall 2004 25

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