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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 86 Hardware micro-task synthesis micro-task datapath legends: Solid black lines: data wires Solid red lines: Ctrl. Wires (ctrl. Inputs from FSM) Dotted red lines: Ctrl. Wires (ctrl. Outputs to FSM) : input Ctrl.Port : output Ctrl.Port : input DataPort : output DataPort C2D :Ctrl.toDataBuffer ioDSel0 gVMW ioPortW gVMASel0 ioDSel1 aluOut gvRamOutPad ioWePad gVMASel1 gVMDirAdr q C2D gVMDirAdr op1Sel0 rfInSel0 op2Sel1 rfInSel1 gVMW gVMASel1 op2Sel0 rdDstAdr aluOp rdSrcW gVMDSel cIn op1sel1 Ctrl. FSM rdDstW gVMASel0 cOut Lt_GT0 rdSrcAdr Lt_GT1 ioPortAdr Lt_GT2 ioDSel0 ioPortW immRAdr ioDSel1 ioDInPad gVRamWePad regSrc IO Module q regSrc ioPortAdrPad immROut regDst 8 gvRamOutPad ioPortAdr 6 C2D gVRamAdrPad gVMDSel ioDOutPad op2Sel0 gVRamInPad (dp) regDst 8 ioDOutPad (dp) op2Sel1 aluOut Figure 4.6: Detailed architectural template of a hardware micro-task. immROut immROM (size=2 p ) 8 p P1 C2D immRAdr 8 cOut ALU op1Sel0 aluOut 8 Lt_GT0 Lt_GT1 Lt_GT2 rfInSel0 op1Sel1 rdSrcW 3 regSrc 8 P2 aluOut rfInSel1 8 aluOp cIn Reg. File (size=2 n ) regSrc rdDstW Op name add not cmp and or xor shl shr aluOp2 0 0 0 0 1 1 1 1 aluOp1 0 0 1 1 0 0 1 1 aluOp0 0 1 0 1 0 1 0 1 P1 8 regDst immROut 8 rfIn n memOp n rdDstAdr C2D C2D rdSrcAdr

tel-00553143, version 1 - 6 Jan 2011 Proposed design-flow for micro-task generation 87 FSM.vhd Task.c Compiler Front-end Tree-based Instruction Selection and Mapping Register Allocation FSM Generation Micro-Task Synthesis Design- Flow CDFG-Level IR Assembly-Level IR Bitwidth Adaptation Assembly-Level IR Datapath Generation EMF-based RTL-Models for FSM and Datapath Code-Generation Tool Datapath.vhd Custom Datapath Model Figure 4.7: Design methodology for hardware micro-task generation. This section details our proposed software design-flow used to generate these customized hardware micro-tasks from an application description written in C (shown in Figure 4.7). A comparison of our approach to classical HLS/ASIP-design flow is presented later in this section. We have identified six distinct steps involved in the design-flow for micro-task synthesis that are explained in the following sections. 4.2.1 Compiler front-end Our flow begins with the front-end compilation of the ANSI-C specification of an application. This first step transforms the input description into a formal Intermediate Representation (IR). This step benefits from several target-independent code transformations such as constant evaluation and propagation, single static assignment, loop unrolling, etc. The output of this step is an IR (that is in the form of a CDFG) in

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