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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 88 Hardware micro-task synthesis for loop while loop Figure 4.8: Example of a CDFG generated through GeCoS [86]. which instructions are represented as trees. This part of our design-flow is based on the front-end of the GeCoS [86] retargetable C-compiler, initially developed by L’hours. Figure 4.8 presents a generic example of the CDFG generated by GeCoS front-end where different sub-components like basic blocks, composite blocks, while, if, and for blocks can be observed. GeCoS can represent instructions present in a basic-block either as expression-trees or DAGs. In this work, we use tree-based intermediate representation. 4.2.2 Instruction selection and mapping The tree-based IR represents each basic operation (e.g. memory fetch or store, addition or subtraction, conditional jumps, etc.) by a tree node. A real machine instruction often performs several of these basic operations at the same time. For example, a mac instruction can perform addition and multiplication in a single step. On the other hand the situation can be reversed i.e. a basic operation in an IR (e.g. a 32-bit memory fetch) can be mapped to a sequence of several machine instructions (4x 8-bit load instructions). Finding the appropriate mapping of machine instructions to a given IR-tree is done through an instruction selection phase. As mentioned previously, even if there exist more sophisticated approaches for in

tel-00553143, version 1 - 6 Jan 2011 Proposed design-flow for micro-task generation 89 /* The syntax of a BURG rule defined in our BURG generator is: Symbol : Pattern {Cost computation} = {Action} */ stmt: SET(REGISTER, ADD(reg8, mem)) { if (!isByteType($value[4])) return false; // this expression defines the cost (C) of this BURG rule $cost[0] = $cost[4] + $cost[5] + 2; } = { // this block defines the action (A) of this rule }; AsmInst add = new AsmInst (“addBG”, 0, 3, false); add.addOperand ($action[4] ()); add.addOperand ($action[5] ()); block.addInstruction(add); return; Figure 4.9: A sample BURG rule being used in our BURG-generator. struction selection (e.g. instruction selection on DAGs [76, 83, 91]); our current implementation uses a simple BURG-based tree-covering algorithm to provide a polynomial time solution to the instruction selection problem as we target control-oriented applications where there is very little instruction-level parallelism. Moreover, the polynomialtime solution of instruction selection problem makes the tool useful for real-life applications that is also an important factor in our point of view. The approach is based on the work of L’hours who used the tree-based pattern matching to generate retargetable ASIP instruction-set architectures (ISAs) [86]. 4.2.2.1 Customized BURG-generator Following a similar approach as was used by Proebsting in [114], we used a back-end compilation tool called BURG-generator. The input to the BURG-generator is a set of rules of the form R = (P, S, C, A) where P is a pattern existing in the CDFG (IR), S is the replacement symbol, C and A are the cost and action taken if the given rule is selected. Figure 4.9 shows a sample BURG rule that is being used by our BURGgenerator. Each of the terms used in a BURG rule and its difference from the conventional BURG-generator approach is explained in the following paragraphs. P , the pattern: Each rule in the BURG-grammar defines an instruction pattern that can be used to cover a given expression-tree if that rule is selected. Since most of the workload of a traditional WSN-based MCU consists of the communication with its RF-transceiver or sensor through SPI-interface [119], we define such a template for hardware micro-task datapath where memory and I/O modules can directly work as operands for ALU and direct interaction is possible between register-file, data memory

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