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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 90 Hardware micro-task synthesis that carries the global shared variables, I/O modules and immediate ROM that carries the constant values (as shown in Figure 4.6). In order to better exploit this datapath, we do not limit ourselves to simple ISAs (such as MIPS, RISC or mini-MIPS) but generate relatively complex instruction patterns and their corresponding rules in our BURG-generator, so as to obtain an efficient covering. S, the replacement symbol: The second entity defined in a rule is S, the replacement symbol. S is normally a nonterminal and an instruction pattern described in a given rule is reduced to the nonterminal defined by that rule. We differ, in the definition of the replacement symbol, than the normal BURG-based instruction selection as we introduce typed-nonterminals that result in the generation of an assembly-level IR having typed-pseudoregisters. The nonterminals used in our grammar are stmt, reg8, reg16, reg32, mem, and cond. Apart from nonterminals, our grammar contains terminals that represent the operator-nodes in an expression tree. Some examples of these terminals are SET, ADD, SUB, XOR, AND, OR and CMP that correspond to assignment, addition, subtraction, exclusive-OR, AND, OR and comparison operations in a tree-based CDFG. C and A, the cost and the action: C and A are the cost and resultant action taken, if the given rule for instruction selection is used. A can be, for instance, the resultant machine instructions generated if the concerning rule is selected for the given pattern. As the operating frequency for WSN applications is quite low (current low-power MCUs work at around 1 MHz to 4 MHz), the time available during a single clockcycle is long enough to perform several operations. We exploited this fact and our instruction selection tries to minimize the total number of clock-cycles consumed during the execution of an input IR instruction. Since the complex patterns mentioned-above involving the memory- or I/O-operands result in a lesser number of overall clock-cycles, the code selector generates these specialized instructions (involving mem- and I/O-operands), instead of generating multiple simple reg-reg-type instructions that involve additional load and store instructions to move the data from I/O-peripherals and memories to the register file. The idea is illustrated with the help of an example in Figure 4.10. The input CDFG pattern is SET(INDIR(INT), AND(INDIR(INT), INT)). This pattern can be covered by multiple rules present in our BURG-grammar. One of these rules corresponds to a complex pattern, which can be executed by the hardware micro-task datapath in only two clock-cycles (as shown in Figure 4.10, Case A). The same input pattern could have been covered by simpler patterns that would have resulted in a sequence of reg-reg, load and store instructions consuming 5 clock-cycles (as shown in Figure 4.10, Case B).The example clearly shows that the selected specialized pattern has a lower cost in terms of execution time. As mentioned earlier, the BURG-rules are defined according to the underlying

tel-00553143, version 1 - 6 Jan 2011 Proposed design-flow for micro-task generation 91 (Case A) Assembly-level IR generated using the specialized I/O-operand-based pattern time Input CDFG IR Instruction: andIOi #ioPort, #const ioPortW

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