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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 94 Hardware micro-task synthesis during bitwidth adaptation, we have to properly increment the pseudoregisternumber according to its type during instruction selection and assembly-like IR generation. � Conversion of comparison operation: The compare operation can also be a difficult problem while performing bitwidth adaptation as comparison of two 32-bit operations cannot be directly replaced by a sequence of four 8-bit comparisons as the compare operation is accompanied by a branch operation. To explain the issue with the help of a simple example, we consider an instruction cmpLL rLong_3, rLong_9 where rLong_3 and rLong_9 are 32-bit pseudoregister. If we want to convert this 32-bit instruction to its equivalent sequence of 16-bit instructions, we need to replace each of two 32-bit pseudoregisters present in the instruction by two 16-bit registers (as shown in Figure 4.12, Case A). The contents of rLong_9 are supposed to be in two adjacent locations in register-file i.e. r10 and r9 while the contents of rLong_3 are at r4 and r3. Then, we perform the compare operation on r4 and r10 that contain the higher 16-bits and depending on the result, we perform the branch operation and then, we add the compare operation of the lower 16-bits using r3 and r9 and add the proper branch operation afterward. Moreover, the conversion of the compare operation involving operands of different bitwidth has to be handled differently. The procedure used in our bitwidth adaptation phase is shown in Figure 4.12(Case B) where we are comparing a 32-bit operand (rLong_3) with a 16-bit operand (rInt_9). We, at first, compare the higher 16-bits (i.e. the contents of r4) with 0. Then the branch operation is appended that will be performed depending upon the result of compare and then the compare operation having the lower 16-bits of first operand (i.e. the contents of r3) and the second operand (r9) is performed and its corresponding branch operation is added afterward. Similar transformations are also used during the bitwidth adaptation of the Shift Left and Shift Right operations. For instance, a 32-bit shliL instruction is replaced with a sequence of one 8-bit shl and three 8-bit shlc instructions to propagate the carry in sequential shift operations. 4.2.4 Register allocation The only explicit resource binding operation performed in our design-flow is register allocation. In this step the temporary pseudoregisters used during the instructionselection phase are replaced by physical registers present in the register-file of our micro-task datapath. We used a similar register allocation approach as was used by Chaitin et al. [18]. We used a linear approximation based algorithm to implement the graph coloring algorithm. However, we do not implement the register-spilling step during the register allocation at the moment. Since the number of registers available in a register-file of our

tel-00553143, version 1 - 6 Jan 2011 Proposed design-flow for micro-task generation 95 cmp rLong_3, rLong_9 ble B23 32-bit rLong_3 r4 r3 16-bit 16-bit 32-bit rLong_9 r10 r9 16-bit 16-bit cmp r4, r10 blt B23 cmp r3, r9 ble B23 cmp rLong_3, rInt_9 ble B23 32-bit rLong_3 r4 r3 16-bit 16-bit 16-bit Case A Case B #0 cmpi r4, #0 blt B23 cmp r3, r9 ble B23 16-bit rInt_9 Figure 4.12: Bitwidth adaptation of the compare and branch instructions. hardware micro-task is customizable, we gradually increase the number of physical registers during register allocation if the previous value results in an allocation failure. It turns out that the number of registers required for allocation in WSN-related applications remains quite small (ranging from 2 to 8, as will be seen in Chapter 6). Nevertheless, register spilling may be implemented, in future, to generate a hardware micro-task datapath with a maximum fixed size of register file and the trade-offs would be studied for power/area/energy consumption comparison between a larger register file and a larger external data memory carrying the data of the spilled registers. 4.2.5 Hardware generation The machine-specific IR obtained after register allocation is then processed through the FSM and datapath generation tools to generate an RTL-level IR of the hardware microtask. The main reason for using this RTL-level IR is its reusability for code generation facilities. Once the RTL-level IR is generated, it can be easily retargeted to generate different back-end descriptions, such as VHDL, SystemC and C (for C-based behavioral simulator of the hardware micro-task that is discussed later in Section 4.2.5.3). There are two parts of the hardware micro-task RTL-level IR (i) a semi-custom datapath (ii) an FSM, in which each machine-specific instruction, present in the assemblylike IR, is mapped to a sequence of micro-code (i.e. FSM states) used to control the micro-task datapath. The hardware generation phase for each of these two components is discussed in the following sections. 4.2.5.1 Datapath generation We have developed, using the“Eclipse Modeling Framework (EMF)”[134], an RTL-level template for a generic datapath that can be used to construct an RTL-level IR of any circuit such as an FFT, DCT or FIR. This template contains the RTL models for wires, r9

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