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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 98 Hardware micro-task synthesis There are several back-end passes developed for the generation of different output representations of the control-flows described in FSM-Sequencer. For example, an RTLlevel IR description for the FSM can be generated. This RTL-level IR for the FSMs can be integrated in the RTL-level IR of datapath to complete the RTL-level IR of the complete hardware micro-task. Similarly, we can also generate the C and SytemC descriptions for the control-flows written in FSM-Sequencer. We created a back-end pass that takes the low-level assembly-like IR generated after the register allocation and generates a control-flow description in FSM-Sequencer. Each control-sequence of this control-flow carries the micro-coded control signals for the underlying micro-task datapath. Above-mentioned code generation tools are then used to generate the corresponding RTL-level IR for different FSM components such as states, transitions, inputs and output ports. 4.2.5.3 Code generation The Eclipse Modeling Framework (EMF) provides code-generation facilities that can be used to write back-end templates for different output codes (such as VHDL and SystemC). We use these facilities to write the VHDL templates for all the library components present in the RTL-level generic datapath template such as the FSM, the dual-port RAM, the single-port ROM, the ALU block and the multiplexers etc. In the last step of our design-flow, using these VHDL templates for datapath and FSM components, we generate VHDL description for the hardware micro-tasks described in the RTL-level IR. Similarly, we used the code generation facilities to write the C-based simulator templates for the assembly-like IR of the hardware micro-task code to perform the cycleaccurate behavioral simulation of the micro-tasks. A C-based behavioral simulator is used to simulate the behavior of a circuit in C. It can be used to perform debugging and behavioral validation of the circuit. There exist C-based Instruction-Set Simulators (ISSs) for different low-power MCUs (such as the MSP430 and the AVR) and some of them are also integrated in the WSN-node and network simulators (such as WSim [62] and WSNet [63]). This cycle-accurate micro-task behavioral simulator could serve for early validation and debugging of the hardware micro-task synthesis design-flow. Moreover, the generated simulators would also be integrated (in the future) in WSim and WSNet for a complete system-level and network-level validation. 4.2.6 Comparison to traditional design-flows of ASIP and HLS Our design-flow is a hybrid of traditional ASIP and HLS design-flows. In traditional HLS, there is no notion of instruction pattern selection and mapping but an FSMbased controller is directly generated after analyzing the application code. On the contrary, our tool based on a retargetable compiler performs the instruction selection and mapping similar to a retargetable ASIP-like compiler infrastructure. Moreover, in traditional HLS, the tool is provided with a library of available hardware components and it generates itself a datapath based on an iterative approach. In contrast, similar

tel-00553143, version 1 - 6 Jan 2011 Proposed design-flow for micro-task generation 99 (a) FSM representing consecutive control-sequences described in FSM-Sequencer set rfInSel0=true, rfInSel1=false, immRAdr=0; set rdDstW=true, rdDstAdr=2; set aluOp0=false, aluOp1=false, aluOp2=false, op1Sel0=false, op1Sel1=false, op2Sel0=false; B4_1 -rfInSel0

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