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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 100 Hardware micro-task synthesis HLS flow ASIP synthesis flow LoMiTa design-flow Datapath (DP) selection Iterative (mostly) User-guided (ISA based) User-guided (ISA based) Instruction selection No Yes Yes Hardware generation FSM + DP ISA-based processor FSM + DP Application domain Compute-intensive Compute-intensive Control-oriented Table 4.1: Comparison of major features of the proposed approach to the existing ones. to “UGH” approach proposed by Augé et al. [10] that uses a datapath-level abstraction to help coprocessor generation, our tool is provided with a higher-level (instruction-set level) abstraction to help the hardware micro-task synthesis. In addition, our approach may seem similar to the processor specialization of Gorjiara et al. [11], however, our main goal is to minimize the silicon footprint of the resulting hardware micro-task, improving performance is only a secondary objective. As far as comparison to ASIP design-flow is concerned, our tool performs the instruction selection and mapping but does not follow the classical object-code and processor synthesis path. Instead it generates a micro-coded FSM that is used to control the micro-task datapath. Table 4.1 compares some of the major features of the three design-flows. The hardware micro-tasks generated through our design-flow show good results in terms of not only power and energy consumption but area cost as well. The details of experimental setup, application benchmarks and a practical case-study are presented in Chapter 6. However, the next section provides some results for a control-oriented task processed through our micro-task generation tool. 4.3 An illustrative example of micro-task synthesis As it has been discussed by Raval et al. [119], major part of a WSN node workload consists of communicating with the RF transceiver for data exchange. This dataexchange is normally performed between the on-chip MCU and the RF transceiver through SPI-link. In this section, we present a small example of a C-code to explain the working of our design-flow. This C-code is a function called sendBeacon() that is used by a receiver WSN node to send a beacon-frame to a transmitter node through its RF transceiver. A part of this particular C-code is shown in Figure 4.15. Since this application code contains the instructions that directly communicate with the I/O ports of an RF transceiver, we will take this opportunity to show the specialized instruction selection of our tool to select the I/O-operand based instructions. We have highlighted the portion of C-code that will be concentrated upon throughout this example. The input C-code is processed through the GeCoS front-end and an IR in the form of a CDFG is generated (as shown in Figure 4.16). This CDFG (IR) is then processed through instruction selection, bitwidth adaptation and register allocation phases, and a low-level assembly-like IR is generated. Figure 4.17 shows the IR that corresponds to

tel-00553143, version 1 - 6 Jan 2011 An illustrative example of micro-task synthesis 101 for (i = 0; i < 8; ++i) { (*(volatile unsigned char*)0x04) = sentFrame[i]; while (((*(volatile unsigned char*)0x02) & 0x01) == 0); } /**************************************************/ // The part of the C‐code under study that communicates // with the I/O‐ports addressed by 0x01 and 0x04 (*(volatile unsigned char*)0x01) |= 0x01 ; (*(volatile unsigned char*)0x01) &= ~(0x01); (*(volatile unsigned char*)0x04) = 0x03; /***************************************************/ while (((*(volatile unsigned char*)0x02) & 0x01) == 0); (*(volatile unsigned char*)0x01) |= 0x01; do { (*(volatile unsigned char*)0x01) &= ~(0x01); (*(volatile unsigned char*)0x04) = 0x00; while (((*(volatile unsigned char*)0x02) & 0x01) == 0); } spiStatusByte = (*(volatile unsigned char*)0x03); (*(volatile unsigned char*)0x01) |= 0x01; Figure 4.15: A portion C function sendBeacon() under study. the C-code under study. Here, we can clearly see the I/O-operand based specialized instructions such as orIOi and movIOi being generated. This IR is then processed through the hardware generation stage of our tool and it is converted to its corresponding RT-level EMF-based model of a hardware micro-task that is further processed through the code-generation step to generate the synthesizable VHDL description. 4.3.1 Resultant dynamic power and energy savings We present below a comparison of power and energy consumption of sendBeacon() task when implemented in hardware (generated through our tool) and in software on a low-power MSP430F21x2. The original C-code for sendBeacon() when run on the MSP430-core consumes on average 278 nJ for one execution while working at 16 MHz. The equivalent hardware micro-task generated through our tool, for 130 nm technology, consumes only 1.4 nJ of energy for one execution while working at same frequency. As far as, the power consumption is concerned, the MSP430-core consumes around 8.8 mW when working at 16 MHz while the equivalent hardware micro-task consumes approximately 33 µW. As a result, we get a 264 x power while 198.5 x energy gain respectively while executing the same control task in hardware generated through our tool. More details of our experimental results are presented in Chapter 6).

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