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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 102 Hardware micro-task synthesis Figure 4.16: CDFG representation of the C-code under study.

tel-00553143, version 1 - 6 Jan 2011 An illustrative example of micro-task synthesis 103 B27: B23: jmp B26 addi %r0, #1 jmp B22 /**************************************************************/ // B30 corresponds to the highlighted part C-code in Figure 4.15 B30: orIOi %io0(#1), #1 andIOi %io0(#1), #0 movIOi %io0(#4), #3 /*************************************************************/ B31: B32: B34: B36: movi %r1, #2 movi %r0, #1 and @(%r1), %r0 movi %r0, #0 cmp @(%r1), %r0 bne B34 jmp B31 orIOi %io0(#1), #1 movIOi %io0(#1), #0 movIOi %io0(#4), #0 Figure 4.17: Machine-specific intermediate representation of the C-code under study. As we discussed in Chapter 1, our work consists in a complete design-flow for the generation of ultra low-power WSN-node controllers. On one hand, our design-flow consists in a C to RTL VHDL generation of hardware micro-tasks, while on the other hand, the second contribution of our work consists in developing a design-flow for the generation of a hardware System Monitor (SM) that is responsible for the scheduling of these hardware micro-tasks. Next chapter presents the details about the notion of our system-level execution model and its features, the corresponding existing work as well as the design-flow for the synthesis of the SM responsible of implementing this system-level execution model.

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