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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 116 Proposed system model and design-flow for SM synthesis high level of specialization within the parent task. The data communication between the parent and the child hardware micro-task is done through shared memory. 5.4.4 Memory management There are small locally shared memories used by the hardware micro-tasks that can be power-gated once their corresponding micro-tasks are shut down. We must emphasize that a system-level model (see Section 5.6) is used to specify that, after the termination of a given task, which memory was being used by the task and this information is used to turn the shared memories off. This notion of small power-gated locally shared memories, instead of a large global one, will also contribute to the overall reduction in power consumption. There is also a very small global memory (based on non-volatile flash technology) that is used to store the global data such as the node-ID, node-address, neighborhood table and if there is some potential data to be saved by the micro-tasks, in case of local memory shut-down. Since an always-ON memory can be critical from the point of view of static power dissipation, we use a non-volatile flash memory to store the needed data that can be turned-off in case of total node shut-down. In this extremely low-power mode, only the SM will be powered-on while all the other components of the micro-task-based computational and control subsystem will be power-gated. In the next section, we explain the architecture and working of the SM being used for task- and power-management. 5.5 System monitor (SM) All the features presented in previous section are made sure by a hardware scheduler present in our system, called the System Monitor (SM). The SM that is responsible for powering-on/off micro-tasks/memory blocks upon reception of an (or a combination of) event(s), is itself implemented as a simple combinational logic block to evaluate the guard conditions for micro-task activation and a set of 1-bit status registers carrying the state of events and commands signals until they are used by micro-tasks. Figure 5.7 provides a block diagram of the SM components for the case study example mentioned in Section 5.1.3. In our execution model, we restrict ourselves to micro-tasks following a run-tocompletion semantic, as in the case of TinyOS tasks. This ensures that a given microtask will never reach a state in which it is activated (i.e. its powered-on) while not executing useful computation (i.e. blocked waiting for some event). In addition, we make sure that at a given time instant there may not be two active tasks sharing a write-access to a same shared resource. This property is ensured (in a conservative way) by the SM which makes sure that, prior to activating a candidate hardware micro-task, there are no other active micro-tasks that may need write-access to a resource that may also be used by the candidate micro-task. In the remaining part of this chapter, we will explain the design-methodology that

tel-00553143, version 1 - 6 Jan 2011 Design-flow for the SM generation 117 RR Q R Q R Q R Q R Q S S S S S S Event Registers event_1 event_2 event_3 event_4 event_5 System Monitor Combinational Logic S R S R S R S R S R Q Q Q Q Q Status Registers en_MT1 en_MT2 en_MT3 en_MT4 en_MT5 MT5 System Monitor Figure 5.7: Block diagram of the System Monitor designed for the lamp switching example of Figure 5.3. we have devised for the automatic synthesis of the SM from a high-level system description. 5.6 Design-flow for the SM generation Figure 5.8 shows the second half of our tool, a design-flow developed for the generation of the SM that is used to control the system-level behavior of a micro-task-based WSN node. The basic steps involved in this design-flow are discussed in details in the following sections. 5.6.1 System specification We developed a Domain Specific Language (DSL) that is used to specify the system-level execution model of a WSN node and its components e.g. micro-tasks, event, shared memories, peripherals, etc. This DSL is developed by using Xtext, the EMF-based MDE framework. In order to write a system-level description of a micro-task-based node, we have to define all the external and internal events present in the system. Moreover, for each micro-task in the system, we specify its corresponding sub-program name, the event configuration (whether a single event or a logical combination of events) that is necessary for the micro-task activation and also the events produced by the micro-task at its termination. Similarly, for each global variable of the application-code, we specify which memory block (gated/non-gated) is used as storage component and the shared I/O ports that are used by the micro-task. Figure 5.9 shows an example of the system-level description written in DSL. This description corresponds to a portion of the lamp-switching example shown in Figure 5.3,

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