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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 120 Proposed system model and design-flow for SM synthesis where the important notions of the execution model such as events, shared resources and micro-tasks are highlighted. 5.6.2 Model transformation In the second step of the design-flow, the information provided by the system specification is processed through our tool and an IR of the system is generated that contains the EMF-based models of all the important components of our system model such as the events, the hardware micro-tasks, the shared memory as well as the I/O modules. This EMF-based IR is also connected to the EMF-based IR (CDFG) of the microtask synthesis design-flow for the retrieval of necessary information such as the global variables and I/O port addresses. 5.6.3 Extraction of guard expression for micro-task activation Using all these pieces of information present in the IR, we derive the guard expression for each micro-task activation present in the system. In simple form, a micro-task TN can only be activated when the following conditions are met: � All the internal and external event signals present in TN’s event configuration (or their logical combinations) are evaluated to true. � The event signals (or their logical combinations) present in the event configuration of a task TM are false where TM is such a micro-task that is sharing a write-access with TN to a memory or I/O resource. Using the above mentioned conditions, we derive the following guard expression for a micro-task TN’s activation: CGN = EAN &∀TM not(EAM )&∀TI not(EAI ) (5.1) where EAN is the event configuration for TN activation, TM is a micro-task sharing a write-access with TN to a memory resource and TI is a micro-task sharing a writeaccess with TN to an I/O resource. The command signals, generated by combinational logic (see Figure 5.7), that are used to control the status registers are evaluated by the guard expression derived above. The status registers are in turn connected to the power-gating ports of the corresponding hardware micro-tasks to control their activation/deactivation. 5.6.4 Hardware generation In the final step, using the guard expressions evaluated for different micro-tasks and shared memories, an RTL EMF-model of a datapath is generated following the generic template given in Figure 5.7. This model contains the combinational logic for microtask/memory activation, a set of 1-bit status and/or event registers that store the

tel-00553143, version 1 - 6 Jan 2011 Experimental results of the SM generation design-flow 121 signals until used by the micro-tasks, and I/O pads to communicate with different components of the system (such as micro-tasks, shared resources and I/O peripherals generating the events). This EMF-model of the SM datapath is then processed through the facilities for code generation provided by the framework (e.g. the JET editor) to generate a synthesizable VHDL description for the SM. 5.6.5 C-simulator generation for early system validation To speed-up the system-level validation of a micro-task-based WSN node, we have used our design-flow to generate a C-simulator for the SM. This C-simulator can be integrated with the C-codes of the WSN application and can work for an early validation and debugging for the SM-synthesis design-flow. Just to demonstrate the power and area consumption of a generic SM generated through our design-flow, a simple example is presented in next section. 5.7 Experimental results of the SM generation designflow The detailed experimental validation of our design-flow in presented in Chapter 6 with the help of a case-study. However, just to demonstrate how light-weight an SM can be in terms of power and area, we wrote the system description of the TFG shown in Figure 1.4 in our DSL. We then processed this system through our tool and generated a VHDL description of the hardware SM that controls the activation/deactivation of the four micro-tasks and the shared memory. We then synthesized this VHDL description for 130 nm process technology and got its static and dynamic power consumption as well as the area overhead. According to the results, the SM hardware consumes 5.15 µW of dynamic power while operating at 16 MHz and a mere 296 nW of static power while using standard cell libraries at 1.2 V. The static power consumption can be further reduced to 80 nW if low-power cell libraries working at 0.3 V are used for 1-bit registers present in the hardware (see Figure 5.7). As far as the area overhead of the SM is concerned, it take only 754 µm 2 that corresponds to just 1% of the surface area consumed by an MSP430-core synthesized using the same process technology. Next chapter contains further details about the experimental setup, the application benchmarks as well as our methodology for comparing the power/energy benefits of the proposed approach over a conventional MCU-based WSN-node.

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