tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 122 Proposed system model and design-flow for SM synthesis

tel-00553143, version 1 - 6 Jan 2011 Chapter 6 Experimental setup and results This chapter presents the experimental setup and the results that we have achieved. It starts by describing the effects of using power-gating technique in our system and improvement achieved in wake-up response time. It then covers the dynamic and static power reductions obtained by our approach as compared to the currently available lowpower MCUs in the light of a case study WSN application. Additionally, it provides the findings based on the design space exploration that we performed by varying the sizes and bitwidths of the micro-task datapath components and summarizes the optimal option. This chapter also provides the results for the power consumption of a hardware SM controlling the micro-tasks present in the case study and compares them with a soft-core MCU-based solution. The chapter finally concludes with the analysis of overall energy gain obtained while using power-gating over an entire period of a power-gated micro-task activation. 6.1 Power-gating and resultant switching delays To check the applicability of power-gating in our proposed node architecture, we used a similar model of power-gated blocks as was used by Hu et al. [59]. However, as the authors did not provide any quantitative data for the switching delays specific to a CMOS technology, we had to re-run the experiments. For this purpose, Eldo from Mentor Graphics was used to perform the transistorlevel SPICE simulations using a 130 nm CMOS technology at a supply voltage of 1.2 V 1 . We used parallel NAND gates to model the timing behavior of a gated block (as shown in Figure 6.1). We observed a linear relation between the number of gates to be powergated, n and the gating-transistor width, W . Similarly, a linear relation between n and output switching delays of the circuit was observed if the width of the gating-transistor was kept constant. Figure 6.2 shows this relation for a transistor width of 2.04 µm. It means that we are constrained on the number of gates to be driven by a single gating-transistor, if the switching delays are to be kept small. 1 At that time, the design kit in 65nm was not available in the Lab. 123