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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 130 Experimental setup and results sends an acknowledgment frame to its RF transceiver and generates a ackSent event. � Switching the lamp: The next task, in receiver TFG, is switching the lamp that is accomplished by calling the switchLamp() function. This function analyzes the previous state of the lamp by reading its corresponding port and inverses it to switch the lamp state. Then it generates a lamp Switched event. � Shutting down the transceiver: Upon reception of lamp Switched or timeOut NoData event, the receiver node shuts down its RF transceiver to conserve energy until the next periodic wake-up event. All the tasks present in the TFGs of this case-study were processed through hardware micro-task synthesis design-flow to generate hardware micro-tasks of two different bitwidths (8-bit and 16-bit). The resultant VHDL descriptions for the specialized hardware were synthesized through back-end commercially available synthesis tools. In next section, we discuss the synthesis results obtained during our experiments. 6.3 Dynamic power gains The hardware micro-task (FSM + datapath) VHDL descriptions have been synthesized for both 130 nm and 65 nm CMOS process technologies using Design Compiler from Synopsys. We used these synthesis results to extract gate-level static and dynamic power estimations where an operating frequency of 16 MHz was assumed. These results were compared to the power dissipated by two different versions of MSP430 MCU: � tiMSP, the Texas Instruments MSP430F21x2. We used the datasheet information for its power consumption (8.8 mW @16 MHz in active mode) which includes memory and peripherals, � openMSP, an open-source MSP430-core without accounting for program memory, data memory and peripherals. We synthesized it and did the statistical power estimation for 130 nm technology and found it to be 0.96 mW @ 16 MHz. We expect the actual power dissipation of the MSP430-core along with its program memory to lie somewhere in between the two results, and compare our results to both of them. The results are given in Table 6.1 through Table 6.5. Table 6.1 shows the machineinstruction and cycle count, time taken, power and energy consumption for both tiMSP and openMSP (for software implementation). Table 6.2 and Table 6.3 show the power and energy benefits for 8-bit hardware micro-tasks over both the MSP430 implementations for 130 nm and 65 nm technology respectively. Similarly, Table 6.4 and Table 6.5 summarizes the similar results for 16-bit hardware micro-tasks. Before comparing these results, we explain the methodology that we used to extract information about the cycle-count and total execution time.

tel-00553143, version 1 - 6 Jan 2011 Dynamic power gains 131 6.3.1 Extraction of cycle count The MSP430 ISA consists of several complex instructions and addressing modes that have multi-cycle execution time. There are two techniques to profile an application running on an MCU: (i) simulation-based technique and (ii) statistical technique. In simulation-based technique, we use the instruction-set simulator (ISS)) of the MCU under-test that contains a counter to accumulate the number of cycles used by each machine instruction. We then simulate the byte-code contained in the instruction memory to accumulate the cycle count taken by the input code. The approach gives us the exact number of clock-cycles being used by an application code on a certain MCU. In statistical technique, we statistically analyze assembly-level machine-code of the application and estimate an approximate value of cycle count as the exact control-flow of the application (such as the loops and branches) is not explored. We used the statistical approach to get an approximate cycle count of the application codes of the micro-tasks running on an MSP430-core. Since, the application codes of some micro-tasks such as sendFrame(), swithLamp() or receiveFrame() involve communications with the I/O-peripherals (e.g. lamp and RF-transceiver) through I/O-ports, it is difficult to simulate their behavior using an ISS for the MSP430. As a consequence, we statistically added the number of cycles taken by all the machine instructions by analyzing them one-by-one. To handle the control-flow of the application (such as if -blocks and for-loops), we accumulated the cycles taken by both the branches of an if -block and accumulated the clock-cycles taken by all the instructions present in a for-loop for only one iteration. Similarly, the cycle count for the hardware micro-task is also performed using the statistical technique where the number of clock-cycles taken is equal to the number of FSM-states present the hardware micro-task. Finally using this information about the approximate cycle count and a given common operating frequency, the total execution time for a micro-task running on the MSP430 as well as implemented in hardware as a hardware micro-task was estimated. Going back to Table 6.2 through Table 6.5, it can be observed that, for different benchmark applications and OS tasks, our approach gains between one to two orders of magnitude in power and energy consumption. As it was discussed in Section 2.5.3, the other important parameter for a low-power MCU is its energy efficiency in terms of Joules/instruction. The energy efficiency of our approach is discussed in the next section. 6.3.2 Approximate energy efficiency As mentioned by Hempstead et al. [53] that the energy efficiency measurement for the accelerator-based (hardware specialization) implementations are hard to evaluate in terms of Joules/instruction. Hence, they introduced the notion of Joules/task. Similarly, as the hardware micro-tasks generated through our design-flow are also not instruction-set processors, their exact energy-efficiency in terms of “Joules/instruction”

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