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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 134 Experimental setup and results Processor Operating Actual Energy Normalized Energy Process Voltage (pJ/instruction) (pJ/instruction) Technology (V) (@ 0.50 V) SNAP/LE [31] 0.60 75 52 180 RISC-like core [79] 0.50 27 27 65 Charm [123] 1.03 96 23 130 BlueDot [119] NA 26 NA 130 Hardware micro-task 1.20 12.4 2.2 130 Table 6.6: Actual and normalized energy-efficiencies for various ultra low-power WSNspecific processors. Bit Register RAM ROM ALU Power Area Width File Depth Depth Fns. (µW) (µm 2 ) Depth 130 nm 65 nm 130 nm 65 nm 8 4 4 4 8 57 16.76 7635 2159 8 8 0 8 6 49.7 14.17 7038 2093 8 16 0 2 4 69 20.2 11163 3387 8 4 2 2 2 42 12.23 6160 1617 8 16 2 4 6 93 26.8 13098 4034 16 8 0 4 6 99 27.8 13184 4013 16 4 4 4 8 116 34.05 14423 4199 16 16 0 2 4 139.5 40.73 21590 6555 16 4 2 2 2 88 25.62 11715 3251 Table 6.7: Power consumption for datapaths having different design parameters (@ 16 MHz). 6.4 Design space exploration for datapath bitwidth Our proposed software design-flow was used to generate hardware micro-tasks having both 8-bit and 16-bit datapaths to monitor the power savings as compared to commercial MCUs such as the MSP430. We synthesized the customized datapaths of different hardware micro-tasks extracted from the above-mentioned benchmarks. The synthesis was again performed for both 130 nm and 65 nm CMOS technologies and the power and area estimations are given in Table 6.7. 6.4.1 8-bit vs. 16-bit micro-task The application codes under study have different wordlength operations. For example, the application crc16 mostly uses 16-bit wordlength operations while operations in teadecipher and tea-encipher involve 32-bit wordlength data. The rest of the applications under-test use 8-bit wordlength operations. As expected, for application codes, having wordlengths greater than 8-bit, an 8bit micro-task has twice the number of FSM states than a 16-bit micro-task due to the bitwidth adaptation step of our design-flow. However, interestingly the FSM of a micro-task consumes much lesser power than the datapath and power consumption of

tel-00553143, version 1 - 6 Jan 2011 Power estimation of hardware system monitor 135 Power (micro−watts) 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 Number of FSM States Figure 6.6: Power consumption vs. number of states of a micro-task FSM. even very large FSMs increases in a sub-linear fashion with the number of states as shown in Figure 6.6. As a result, an 8-bit micro-task consumes nearly half the power and silicon area than a 16-bit micro-task (Figures 6.7 (a and b)). As far as the energy consumption is concerned, for codes having wordlengths greater than 8-bit, total energy consumption of an 8-bit and 16-bit micro-task is nearly the same. On the other hand, for application codes having 8-bit wordlength, an 8-bit micro-task consumes half of that of a 16-bit micro-task, (as shown in Figure 6.7 (c)). Hence, as the datapath power dominates the FSM power in our case study, an 8-bit micro-task is a better solution. Nevertheless, for cases where FSMs could be comparatively much larger and consume more power than the datapath, micro-tasks having larger bitwidth would become more suitable. 6.5 Power estimation of hardware system monitor To compare the power consumptions and potential area overhead of a hardware system monitor (SM), we wrote a system-level description of the TFGs present in our case-study application using our DSL. Then we used our design-flow for the SM synthesis to process this system-level description and generated an RTL description of the SM controlling the hardware micro-tasks, I/Os and memory modules present in our proposed WSNnode (similar to the one shown in Figure 5.4). 6.5.1 Dynamic power consumption The VHDL description of the hardware SM was synthesized for 130 nm process technology. The results show that it consumes only 12 µW at an operating frequency of 16 MHz and since the average active period of a WSN node is quite low (less than 1% of the overall duty cycle), this power consumption is negligible as compared to an OS-based scheduler running on an MSP430 that consumes between 8.8 mW (tiMSP) to 1 mW (openMSP).

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