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tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 142 Conclusion and future perspectives However, these processors are designed for low-power operation across a wide range of embedded system application settings. As a consequence, they are not necessarily well-suited to WSN node design as they are based on a general purpose, monolithic compute engine. On the software end, WSN nodes generally rely on a light-weight OS layer to provide concurrency management for both external event handling and/or application task management. Eventually, power dissipation of current low-power MCUs still remains orders of magnitude too high for many potential applications of WSN. We believe that the hardware specialization is an interesting way to further improve energy efficiency: instead of running the application/OS tasks on a programmable processor, we propose to generate an application specific micro-architecture, tailored to each task of the application at hand. We proposed such an approach where a WSN node computation subsystem is made of several hardware micro-tasks that are activated on an event-driven basis, each of them being dedicated to a specific task of the system (such as event-sensing, low-power MAC, routing, and data processing etc.). By combining hardware specialization with power reduction techniques such as power-gating, we drastically reduced both dynamic (thanks to specialization) and static (thanks to power-gating) power consumption. In addition, our proposed micro-task-based WSN node contains a hardware scheduler, called system monitor (SM) to perform the task/power-management. The key contributions of this research work can be described as under: � We demonstrated using transistor-level SPICE simulations the potential benefit of power-gated specialized hardware and thus proposed the concept of “power-gated hardware micro-tasks”. � We thus showed that power-gating is applicable to our micro-task-based WSN node architecture and it happens to have very short switching-time delays, in the orders of a few hundred of nano seconds for the larger micro-tasks. This improves the wake-up response time by at least 50% when compared to low-power MCUs such as the MSP430. � We provided an integrated design-flow for the synthesis of micro-task-based WSN node architectures. In this flow, the behavior of each micro-task is specified in C and is mapped to an RTL description of an application specific micro-architecture using a hybrid of retargetable ASIP-synthesis and HLS design methodologies. � We also provided a DSL that can be used to specify the system-level description of WSN node (following an event-driven TFG). The second part of our designflow, using this system-level description, generates hardware description for the SM that is used to control the activation and deactivation of the power-gated micro-tasks present on the WSN node. � With the help of a simple yet realistic case-study of a WSN application, we showed that our approach provides power savings of one to two orders of magnitude in dynamic power when compared to the power dissipation of currently available MCU-based solutions.

tel-00553143, version 1 - 6 Jan 2011 Work in progress 143 � We also used our design-flow to perform design space exploration by exploring the trade-off in power/area that can be obtained by modifying the bitwidth of the generated micro-tasks, and compared the obtained results to those achieved by using an off-the-shelf low-power MCU such as the MSP430. � Using the SM generation design-flow, we demonstrated that the hardware SM generated to control the micro-tasks and shared memories of our case-study application provides 10x reduction in static power and a negligible amount of dynamic power when compared to MCU-based solution. Moreover, the area overhead of a hardware scheduler is only 2% of the surface area of an MSP430-like core. After enumerating the key contributions and results obtained during the course of this work, we take this opportunity to discuss some of the on-going advancements and future perspectives of current research work. 7.1 Work in progress At the moment we are working on two different aspects of this research work. First one is the network-level validation of a micro-task-based WSN node. In our opinion, the generation of a C-simulator for the micro-tasks, that can be integrated in the existing C-simulators for WSN, is among the fastest ways to perform validation and debugging. There exist C-simulators for wireless sensor nodes and networks, such as WSim [62] and WSNet [63] that can be used for this validation. The basic approach is shown in Figure 7.1 where the C-simulators for different low-power MCUs and RF-transceivers are already developed in WSim. We are currently working on adding WSim-compatible C-simulator generation step to our design-flow for micro-task generation. The second issue is the lack of programmability. Our approach has an obvious drawback: it assumes that the micro-tasks are hard-wired into silicon as ASIC blocks. This means that the behavior of each micro-task is fixed, making post-production upgrade or bug fixing very costly. This may look like a show stopper, as flexibility is often of a great concern for WSN system designers. However, when looking more carefully to actual design practices, we can observe that the need of flexibility and reprogrammability is essentially geared toward the user application layer, which happens to represent only a small fraction of the WSN node processing workload, this latter one being almost entirely dedicated to the communication stack. Besides, in practice, designing a new WSN application usually means adapting a proved existing WSN software framework to a new user application. In other words, the communication stack software is generally reused “as is” and routing algorithms, MAC protocols, device driver layers remain the same (even if their behavior is parameterized). We therefore propose to combine the best of both worlds, that is: � use a very small silicon footprint instruction-set processor (8-bit datapath, minimalistic RISC instruction set) with a power-gating feature to implement the application layer user software,

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