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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 146 Conclusion and future perspectives Reconfigurable SoC It will be interesting to study the portability of our approach on control-oriented reconfigurable structures, which would provide support for small grain power-gating techniques. Small grain partial power gating does not exist till now in commercial FPGAs but some work has been done in academics on this aspect [118]. Datapath merging Datapath merging [94] has been used in reconfigurable architecture design to save the overall surface area. It could be interesting to study the feasibility of developing a hardware-OS based MSP430. In such an approach, the designed MSP430-core can work in two modes: (i) general-purpose mode and (ii) specialized mode. In general-purpose mode, the MSP430-core would perform the application-layer tasks of the communication stack. For lower layers of the communication stack, the MSP430-core would be used in specialized mode implementing a hardware-OS where the MSP430-datapath components such as the register file, and the ALU-operators could be used by the hardware micro-task FSMs generated through our design-flow to perform the controloriented tasks such as event sensing, routing, packet processing and forwarding, etc. In this hardware-OS based MSP430, a fine-grain datapath merging could be applied to merge the datapath components present in hardware micro-tasks (generated through our design-flow) and the MSP430-datapath. Since the hardware micro-tasks are power-gated, there will not be any extra cost for adding the multiplexers that are needed at the input of conventional datapath components being merged. With some of the possible future perspectives discussed above, we conclude this manuscript with the publications extracted from this research work.

tel-00553143, version 1 - 6 Jan 2011 Personal publications International conferences � Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys, “System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes”, EuroMicro DSD’10, Lille France, September 2010. � Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys, “A Complete Design- Flow for the Generation of Ultra Low-Power WSN Node Architectures Based on Micro-Tasking”, ACM/IEEE DAC, Anaheim CA USA, June 2010. � Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys, “A Novel Approach for Ultra Low-Power WSN Node Generation”, IET ISSC, Cork Ireland, June 2010. � Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys, “Toward Ultra Low- Power Hardware Specialization of a Wireless Sensor Network Node”, IEEE IN- MIC, Islamabad Pakistan, December 2009 (Best Student Paper Award). � Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys, “Ultra Low-Power FSM for Control Oriented Applications”, IEEE ISCAS, Taipei Taiwan, May 2009. National workshops � Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys, “Ultra Low-Power FSM for Sensor Networks”, GDR SOC-SIP, Paris France, June 2009. 147

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