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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 150 Conclusion and future perspectives FDLS Force Directed List Scheduling FDS Force Directed Scheduling FFT Fast Fourier Transform FGS Fine Grain Scheduling FPGA Field Programmable Gate Arrays FPU Floating Point Unit FSM Finite State Machine FSMD FSM with Datapath GA Genetic Algorithm GeCoS Generic Compiler Suit HAL Hybrid ALlocation HLL High Level Language HLS High Level Synthesis IAPO Interconnect Aware Power Optimized I 2 C Inter Integrated Circuit ILP Instruction Level Parallelism I/O Input/Ouput IR Intermediate Representation ISS Instruction Set Simulator ISA Instruction Set Architecture ISE Instruction Set Extension JET Java Emitter Template LEA Left Edge Algorithm LoMiTa ultra Low-power Micro-Tasking LoS Line of Sight MAC Medium Access Control MCU Micro-Controller Unit MDE Model Driven Engineering MEMS Micro Electro Mechanical System MILP Mixed Integer Linear Programming MIMO Multiple Input Multiple Output MIPS Million Instructions Per Second MOS Mantis Operating System MOSFET Metal-Oxide Semiconductor Field Effect Transistor MTCMOS Multi-Threshold CMOS NRE No Intruction Set Computer NRE Non-Recurring Engineering

tel-00553143, version 1 - 6 Jan 2011 Future perspectives 151 OS Operating System QoS Quality of Service RAM Random Access Memory RF Radio Frequency RICER Receiver Initiated CyclEd Receiver RISC Reduced Instruction Set Computer ROM Read Only Memory RT Register Transfer RTL RT-Level SIMD Single Instruction Multiple Data SM System Monitor SoC System on Chip SPI Serial Peripheral Interface TFG Task Flow Graph UGH User Guided HLS ULIW Ultra Large Instruction Word VHDL VHSIC Hardware Description Language VHSIC Very High Scale Integrated Circuit VLIW Very Large Instruction Word VLSI Very Large Scale Integrated WSN Wireless Sensor Network

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