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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 154 Bibliography ISLPED’04: Proceedings of the International Symposium on Low Power Electronics and Design. ACM, Newport Beach, California, USA, 138–143. [13] Beutel, J., Kasten, O., and Ringwald, M. 2003. Poster Abstract: BTnodes – A Distributed Platform for Sensor Nodes. In SenSys’03: Proceedings of the 1st International Conference on Embedded Networked Sensor Systems. ACM, New York, NY, USA, 292–293. [14] Bhatti, S., Carlson, J., Dai, H., Deng, J., Rose, J., Sheth, A., Shucker, B., Gruenwald, C., Torgerson, A., and Han, R. 2005. MANTIS OS: An Embedded Multithreaded Operating System for Wireless Micro Sensor Platforms. Mob. Netw. Appl. 10, 4. [15] C. A. Mandal, P. P. C. and Ghose, S. 1995. Complexity of Scheduling in High Level Synthesis. VLSI Design 7, 4, 337–346. [16] Cadence. 2010. C-to-Silicon Compiler. Product. [17] Cerpa, A., Elson, J., Hamilton, M., Zhao, J., Estrin, D., and Girod, L. 2001. Habitat Monitoring: Application Driver for Wireless Communications Technology. In SIGCOMM-LA’01: Workshop on Data communication in Latin America and the Caribbean. ACM, New York, NY, USA, 20–41. [18] Chaitin, G. 2004. Register Allocation and Spilling via Graph Coloring. SIGPLAN Not. 39, 4, 66–74. [19] Chandrakasan, A. P., Sheng, S., and Brodersen, R. W. 1995. Low Power CMOS Digital Design. IEEE Journal of Solid State Circuits 27, 473–484. [20] Chang, J. M. and Pedram, M. 1997. Energy Minimization Using Multiple Supply Voltages. IEEE Transactions on VLSI Systems 5, 436–443. [21] Chavet, C., Andriamisaina, C., Coussy, P., Casseau, E., Juin, E., Urard, P., and Martin, E. 2007. A Design Flow Dedicated to Multi-mode Architectures for DSP Applications. In ICCAD’07: Proceedings of the 2007 IEEE/ACM International Conference on Computer-Aided Design. IEEE Press, Piscataway, NJ, USA, 604–611. [22] Chiou, D.-S., Juan, D.-C., Chen, Y.-T., and Chang, S.-C. 2007. Fine- Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization. In DAC’07: Proceedings of the 44th annual ACM/IEEE Design Automation Conference. ACM, New York, NY, USA, 81–86. [23] Choi, E., Shin, C., Kim, T., and Shin, Y. 2008. Power-Gating-Aware High- Level Synthesis. In ISLPED’08: Proceeding of the 13th International Symposium on Low power Electronics and Design. ACM, New York, NY, USA, 39–44. [24] Coussy, P., Gajski, D. D., Meredith, M., and Takach, A. 2009. An Introduction to High-Level Synthesis. IEEE Design and Test of Computers 26, 4, 8–17.

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