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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 160 Bibliography [86] L.L’Hours. 2005. Generating Efficient Custom FPGA Soft-Cores for Control- Dominated Applications. In ASAP’05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors. Washington, DC, USA, 127–133. [87] Long, C. and He, L. 2003. Distributed Sleep Transistor Network for Power Reduction. In DAC’03: Proceedings of the 40th annual ICM/IEEE Design Automation Conference. ACM, 181–186. [88] Mahnke, T., Stechele, W., and Hoeld, W. 2002. Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. In PATMOS’02: Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. Springer-Verlag, London, UK, 146–155. [89] Mainwaring, A., Culler, D., Polastre, J., Szewczyk, R., and Anderson, J. 2002. Wireless Sensor Networks for Habitat Monitoring. In WSNA’02: Proceedings of the 1st ACM International Workshop on Wireless Sensor Networks and Applications. ACM, New York, NY, USA, 88–97. [90] Malan, D., Fulford-jones, T., Welsh, M., and Moulton, S. 2004. Code- Blue: An Ad Hoc Sensor Network Infrastructure for Emergency Medical Care. In BSN’04: International Workshop on Wearable and Implantable Body Sensor Networks. [91] Martin, K., Wolinski, C., Kuchcinski, K., Floch, A., and Charot, F. 2009. Constraint-Driven Instructions Selection and Application Scheduling in the DURASE System. In ASAP’09: Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures and Processors. IEEE Computer Society, Boston, MA, USA, 145 – 152. [92] Mentor Graphics. 2010. Catapult C Synthesis: Full-Chip High-Level Synthesis. Product. [93] Messé, V. 1999. Production de Compilateurs Flexibles pour la Conception de Processeurs Programmables Spécialisés. Ph.D. thesis, Université de Rennes-1. [94] Moreano, N., Borin, E., de Souza, C., and Araujo, G. 2005. Efficient Datapath Merging for Partially Reconfigurable Architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, 7 (jul.), 969 – 980. [95] Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., and Yamada, J. 1995. 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS. IEEE Journal of Solid-State Circuits 30, 8 (aug), 847 –854.

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