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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 166 List of Figures 3.3 List scheduling with deferred operations. . . . . . . . . . . . . . . . . . . 59 3.4 Dataflow graph (DFG) merging. . . . . . . . . . . . . . . . . . . . . . . 65 3.5 Complete UGH design flow [10]. . . . . . . . . . . . . . . . . . . . . . . 66 3.6 NISC design-flow [42]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.7 Design methodology for complete ASIP generation . . . . . . . . . . . . 69 3.8 Design methodology for partial ASIP generation . . . . . . . . . . . . . 70 3.9 Data-flow graph of basic butterfly operation present in an FFT algorithm. 72 3.10 Sample machine instruction template. . . . . . . . . . . . . . . . . . . . 74 3.11 Two possible coverings of the identical tree with different patterns. . . . 74 3.12 Simp1e grammar and its normal form [114] . . . . . . . . . . . . . . . . 75 3.13 Dynamic programming applied to example tree, each node labeled with “(Rule, Cost)”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.1 Design-flow for hardware micro-task generation. . . . . . . . . . . . . . 80 4.2 Architectural simplicity of a hardware micro-task w.r.t. a general purpose CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.3 Generic template of a “micro-task” running in a WSN node. . . . . . . 82 4.4 Architecture of a generic hardware micro-task. . . . . . . . . . . . . . . 83 4.5 Architectural template of customizable ALU block present in hardware micro-task datapath (shown in Figure 4.6). . . . . . . . . . . . . . . . . 84 4.6 Detailed architectural template of a hardware micro-task. . . . . . . . . 86 4.7 Design methodology for hardware micro-task generation. . . . . . . . . 87 4.8 Example of a CDFG generated through GeCoS [86]. . . . . . . . . . . . 88 4.9 A sample BURG rule being used in our BURG-generator. . . . . . . . 89 4.10 Advantage of using specialized pattern that results in an overall reduction in cycle-count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.11 Some grammar rules used by our customized BURG-generator. . . . . . 92 4.12 Bitwidth adaptation of the compare and branch instructions. . . . . . . 95 4.13 Description of a control-flow using FSM-Sequencer DSL. . . . . . . . . 97 4.14 FSM representations generated through our tool for equivalent controlflows described in FSM-Sequencer DSL. . . . . . . . . . . . . . . . . . . 99 4.15 A portion C function sendBeacon() under study. . . . . . . . . . . . . 101 4.16 CDFG representation of the C-code under study. . . . . . . . . . . . . 102 4.17 Machine-specific intermediate representation of the C-code under study. 103 5.1 Design-flow for hardware system monitor generation. . . . . . . . . . . 106 5.2 Different execution paradigms for a WSN node system. . . . . . . . . . 107 5.3 TFGs presenting the tasks running in a lamp switching application. . . 109 5.4 System-level view of a micro-task based WSN node architecture . . . . 109 5.5 System overview of Contiki OS [29] (portioning into core and loaded programs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.6 Access control simplicity of power-gated modules. . . . . . . . . . . . . . 115 5.7 Block diagram of the System Monitor designed for the lamp switching example of Figure 5.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

tel-00553143, version 1 - 6 Jan 2011 List of Figures 167 5.8 Design methodology for system monitor (SM) generation. . . . . . . . . 118 5.9 A snapshot of the system-level execution model, of the lamp-switching example shown in Figure 5.3, described using proposed DSL. . . . . . . 119 6.1 Parallel NAND gates model used to perform the SPICE transistor level simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2 Linear relation between the number of gates being driven by a gatingtransistor and the output switching delay (0 to 1). . . . . . . . . . . . . 124 6.3 Inverse linear relation between the width of the gating-transistor and the output switching delay (0 to 1) for (n = 3000). . . . . . . . . . . . . . . 125 6.4 The output turn-on and turn-off delays for (n = 3000). . . . . . . . . . 126 6.5 TFGs presenting the micro-tasks running during a lamp switching application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.6 Power consumption vs. number of states of a micro-task FSM. . . . . . 135 6.7 Comparison of power, area and energy consumption for 8-bit and 16-bit micro-tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.8 Time distribution of sendFrame task duty cycle. . . . . . . . . . . . . . 137 7.1 Network level validation of micro-task-based WSN node using WSim and WSNet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.2 Proposed solution to tackle the issue of loss of reprogrammability. . . . 145 7.3 System-level view of a micro-task based WSN node architecture . . . . 145

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