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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 22 Introduction network efficiency. Power reduction for computation and control subsystem can benefit from optimizations at several levels of a WSN node design (such as application design, micro-architecture design, logic synthesis and Very Large Scale Integrated (VLSI) circuit design). We will discuss the power reduction techniques adapted at two different levels of a WSN node design, i.e. micro-architectural level and VLSI circuit level as they are the two levels targeted by our approach. 1.2 Power optimization of a WSN node In the last decade, there have been a large number of research results dealing with power optimization in VLSI circuits. A lot of research has also been done to optimize power at micro-architectural level such as evolution of low-power MCUs. This section briefly covers some of these power optimization techniques. 1.2.1 Low-power VLSI design Power dissipation in VLSI circuits can be divided into two categories: dynamic power caused by capacitance switching (i.e. stage changes) that occurs while a circuit is operating and static power caused by leakage current between power supply and ground. When a device is active, its power is usually largely dominated by dynamic power and becomes roughly proportional to clock frequency. However, in the context of WSN, things are slightly different as a WSN node remains inactive for long periods (MCU duty-cycle lower than 1%), and the contribution of static power also becomes significant and can not be ignored. There are several approaches to reduce dynamic power in a circuit (e.g. clock gating, voltage scaling etc.) that can be applied at various levels of the design-flow. However, most of them are poorly suited to WSN nodes as they often significantly increase the total silicon area, and therefore have a negative impact on static power dissipation. One exception is power gating, which consists in turning-off the power supply of inactive circuit components [12, 87]. Power gating helps in reducing both dynamic and static power, and is thus very efficient for devices in which components remain idle for long time periods. The technique consists in adding a sleep transistor between the actual VDD (power supply) rail and the component VDD, thus creating a virtual supply voltage called VV DD as illustrated in Figure 1.2. This sleep transistor allows the supply voltage of the block to be cut off to dramatically reduce leakage currents. 1.2.2 Low-power MCUs As far as the power optimization at micro-architectural level is concerned, a number of low-power microcontrollers (e.g. MSP430, CoolRISC and ATmega128L) have been designed that share several characteristics: a simple datapath (8/16-bit wide), a reduced number of instructions (only 27 instructions for the MSP430), and several power saving

tel-00553143, version 1 - 6 Jan 2011 Proposed approach: combination of power-gating and hardware specialization 23 VG VVDD Block A VDD VVDD VVDD Block B Block C Figure 1.2: An example of power gating. modes which allow the system to select at run-time the best compromise between power saving and reactivity (i.e. wake-up time). These processors, are designed for lowpower operation across a range of embedded system application settings but, are not necessarily well-suited to the event-driven behavior of WSN nodes as they are based on a general purpose, monolithic compute engine. Most of the current WSN nodes are built on these commercial MCUs. For example, Mica2 mote [25] has been widely used by the research community and is based on ATmega128L from Atmel. The same MCU has also been used by the designers of the eXtreme Scale Mote (XSM) [30]. The Hydrowatch [39] and PowWow [64] platforms are built on the MSP430 [129] from Texas Instruments whereas the WiseNet platform from CSEM uses a CoolRISC-core [33] from EM Microelectronic. Although the power consumptions of these MCUs may seem extremely small w.r.t. the power budgets of typical embedded devices, looking at energy efficiency metrics such as Joules per Instruction, it appears that the proposed architectures (such as the MSP430) still offer room for improvement. In particular, it is clear that a combination of specialization and parallelism would significantly help improving energy efficiency. However, such architectural improvements usually come at a price of significant increase in silicon area, which leads to unacceptable levels of static power dissipation for WSN. In the next section, we will discuss our proposed approach that exploits the hardware specialization technique to improve the dynamic power consumption and also tackles the issue of increased static power dissipation using power gating. 1.3 Proposed approach: combination of power-gating and hardware specialization We believe that the hardware specialization is an interesting way to further improve energy efficiency in WSN computation and control subsystem i.e. instead of running the application and control tasks on a programmable processor, we propose to generate an application specific micro-architecture, tailored to each task of the application at hand. This approach results in a drastic reduction of dynamic power dissipation of

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