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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 24 Introduction micro-task Ram Address (Caculated) 2 Ram Input Selection ramDataIn Ram Address (Generated) Shared RAM IFace Register File ROM Arithmetic Logic Unit (ALU) Rom Address en_MT 8 ramDataOut romDataOut 8 Vdd Operand A Adr. Vvdd CTRL. FSM Operand B Adr. rfDataOut 8 8 8 Alu Input Selection Alu Result 3 2 Alu Operand Select Pheripheral On/Off I/O Peripherals IFace Figure 1.3: Architecture of a generic hardware micro-task. a WSN node. On the other hand, to tackle the (potential) increase in static power consumption, we propose to use power gating technique. We propose such an approach where a WSN node architecture is made of several hardware micro-tasks that are activated on an event-driven basis, each of them being dedicated to a specific task of the system (such as event-sensing, low-power MAC, routing, and data processing etc.). The architecture of a hardware micro-task is in the form of a minimalistic datapath controlled by a custom Finite State Machine (FSM) and is being automatically generated from a task specification in C, by using an Application Specific Instruction-set Processor (ASIP)-like design environment retargeted to our purpose. By combining hardware specialization with static power reduction techniques such as power gating, we can drastically reduce both dynamic (thanks to specialization) and static (thanks to power gating) power [103]. 1.3.1 Power-gated micro-task Our approach relies on the notion of a specialized hardware structure called a hardware micro-task, which executes parts of the WSN node code. In contrast to an instructionset processor, the program of a micro-task is hardwired into an FSM that directly controls a semi-custom datapath. This makes the architecture much more compact (neither an instruction decoder is needed, nor an instruction memory) and allows the size of storage devices (register file and RAM/ROM) as well as the Arithmetic Logic Unit (ALU) functions to be customized to the target application. Each of these microtasks can access a shared data memory and peripheral I/O ports (e.g. SPI link to an RF transceiver such as the CC2420 [131]). Figure 1.3 shows the micro-architecture for such a hardware micro-task (here with

tel-00553143, version 1 - 6 Jan 2011 Proposed approach: combination of power-gating and hardware specialization 25 Timer 100 ms Int. Event D Ext. Event T receiveAck MT-D MT-A senseTemp Int. Event C I/O (Temp. Sensor) Temp. Value (Gated Memory-1) Int. Event A sendData processData Int. Event B MT-C I/O (RF Tranceiver) Node ID (Non-gated Memory-2) Neighbor ID (Non-gated Memory-2) MT-B I/O (RF Tranceiver) Temp. Value (Gated Memory-1) Temp. Value (Gated Memory-1) Node ID (Non-gated Memory-2) Neighbor ID (Non-gated Memory-2) Figure 1.4: TFG of a temperature sensing and forwarding application. an 8-bit data-path), dotted lines represent control signals generated by the control FSM, whereas solid lines represent data-flow connections between datapath components. The details of the micro-task architecture are given in Section 4.1.2. 1.3.2 Proposed system model The basic system architecture of a WSN-node based on micro-task-oriented approach and its behavior is explained with the help of a simple temperature sensing and forwarding application in the following paragraphs. Application task graph Consider, for example, an application in which we periodically read the temperature value provided by a temperature sensor through I/O interface, process this value, send it to a neighbor node and finally, receive an acknowledgment from that neighbor node. The task flow graph (TFG) of this application is shown in Figure 1.4 and consists of a set of 4 micro-tasks and some data and control communication. Architecture Figure 1.5 represents the system level view of a WSN node platform designed according to our proposed approach to implement the above-mentioned TFG. Such a system consists of: � A set of power-gated hardware micro-tasks accessing shared resources (e.g. peripherals (RF, sensor) and memories (gated/non-gated)). Each of these hardware micro-tasks is able to perform a specific task such as temperature sensing, data processing etc.

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