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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 26 Introduction Int. Event A Timer En_A Vdd Int. Event B M-Task A M-Task B I/O Port Sensor (e.g. temp) Ext. Event T En_B Vdd Memory M1 Vdd En_Mem_A System Monitor Vdd Vdd M-Task C M-Task D I/O Port Radio chip (ex CC2420) Memory M2 Figure 1.5: System-level view of a micro-task based WSN node architecture. � A hardware System Monitor (SM) that controls the execution of all the hardware micro-tasks. The SM is responsible for the turning-ON/OFF of the hardware micro-tasks as well as the power-gated memories depending upon their usage. � Event triggering peripherals (such as radio, timer etc.) that can send events to the SM. Behavior of a micro-task-based WSN node The behavior of a WSN node based on our approach is simple. There are control signals exchanged between the hardware micro-tasks and the SM. The control signals generated by the SM are called “commands” (e.g. En A, En B, En Mem 1 etc.) as shown in Figure 1.5, whereas signals emitted by the hardware micro-tasks after their job-completion are called “internal events” (e.g. Int.Event A, Int.Event B etc.) shown in Figure 1.5. There are also some events generated by the I/O peripherals that are called “external events” (e.g. Ext.Event T etc.). The behavior of the WSN node, implementing the TFG example shown in Figure 1.4 is explained below: � The SM receives an external event Ext.Event T and through combinational logic implemented in it, it sends the wake-up signal to the power-gated micro-task M- Task A through En A and the power-gated memory Memory 1 through En Mem 1.

tel-00553143, version 1 - 6 Jan 2011 Proposed approach: combination of power-gating and hardware specialization 27 M-Task A wakes up and execute the temperature sensing task by reading the temperature value from temperature sensor through I/O peripheral. This data is then stored in Memory 1. Then M-Task A sends an internal event Int.Event A announcing the SM that it has finished its job. � Upon receiving Int.Event A, the SM shuts down the M-Task A by power-gating its supply-voltage through En A and wakes up the hardware micro-task M-Task B implementing the second task present in the TFG of Figure 1.4. This hardware micro-task reads the temperature value stored in Memory 1, processes it accordingly and stores the new value back in the memory. M-Task B then sends an internal event Int.Event B to the SM announcing its job-termination. � When Int.Event B is read by the SM, it shuts down the M-Task B by powergating En B and wakes up M-Task C that sends the post-processed data stored in Memory 1 to the nearest neighbor. To perform this task, M-Task C also needs the non-power-gated memory Memory 2 that is being used by the node to store its node ID and the neighborhood table. M-Task C performs a simple neighborhood calculation and sends the packet to the nearest neighbor by writing it to the SPI interface of the RF transceiver. M-Task C then sends an internal event Int.Event C to the SM announcing the termination of its job. � Upon receiving Int.Event C, the SM powers down the MTask C by power-gating its supply-voltage through En C and wakes up the hardware micro-task M-Task D implementing the reception of acknowledgment from the neighbor. Since Memory 1 is not needed by M-Task D, it is also power-gated by SM through En Mem 1 line. Finally, once the acknowledgment is received by the node, through successful finish of M-Task D, the SM shuts down the fourth and the last hardware microtask present on the WSN node platform at the reception of an internal event Int.Event D. Resultantly, the whole computation and control part of the WSN node, except the SM and Memory 2, goes to power-off mode to conserve power. 1.3.3 Customized execution model and software design-flow Major portion of this work is devoted to the development of LoMiTa (ultra Low-power Micro-Tasking), a complete system-level design-flow for designing application specific hardware platforms [104, 105]. Following the philosophy of many WSN software frameworks, this flow uses a combination of a textual Domain Specific Language (DSL) for system-level specifications (interactions between tasks, event management, shared resources management etc.) and ANSI-C for specifying the behavior of each micro-task. From such a specification, we are able to generate a synthesizable VHDL (VHSIC Hardware Description Language; VHSIC: Very-High-Speed Integrated Circuit) description of the whole architecture (micro-tasks and SM), which provides a direct path to ASIC or FPGA (Field Programmable Gate Array) implementation. We want to clarify that our goal is not to propose a new model of computation for WSN computation subsystem. We rather see our approach as a simple execution

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