Views
5 years ago

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 28 Introduction model chosen so as to be a good match for what we think is a promising architectural solution for WSN nodes. Here we provide a brief overview of our software framework for designing micro-task based WSN platforms. It consists of two parts: � A customized ANSI-C to hardware compiler which is used to generate the VHDL specification of a micro-task, given its behavior in ANSI-C. � A design-flow that uses a system specification in DSL and generates a VHDL description for its hardware SM. Our complete design-flow is summarized in Figure 1.6: we start from the application task descriptions written in ANSI-C and a system-level description of task interactions described in a textual DSL to derive the behavior of the SM and close the path to hardware generation. The design-flow is based on different Model Driven Engineering (MDE) techniques. To briefly elaborate the concept: the micro-task generation flow is based on Eclipse Modeling Framework (EMF) [134] that is used to define the Register Transfer Level (RTL) EMF-models for FSM and datapath components whereas the SM generation flow is based on Xtext [136] that is used to develop a textual DSL to describe different components of the system-model like micro-tasks, their corresponding events, shared memories and I/O resources. Then the flow uses this description to generate the RTL EMF-models for the SM components. Both of the design-flows, then use the codegeneration techniques to generate the VHDL descriptions for the hardware micro-tasks and the SM architectures.

tel-00553143, version 1 - 6 Jan 2011 Proposed approach: combination of power-gating and hardware specialization 29 Contribution Discussed in Chapter 4 .c .c .c Task C FSM.vhd Task B Task.c Compiler Front-end Tree-based Instruction Selection and Mapping Register Allocation FSM Generation Software Tasks Task A Micro-Task Synthesis Design- Flow CDFG-Level IR Assembly-Level IR Datapath.vhd Custom Datapath Model Application Task A EventA Task B Task C Hardware Micro-Tasks .vhd .vhd .vhd .vhd System Micro-Task C Micro-Task B Micro-Task A Monitor Hardware Synthesis Tool Final IC Bitwidth Adaptation Assembly-Level IR Datapath Generation EMF-based RTL-Models for FSM and Datapath Code-Generation Tool Shared Mem Model Transformation Guard Expression Evaluation Transistor Level Insertion of Power Gating Contribution Discussed in Chapter 5 EventB Proposed Textual DSL for System- Level Description Application.sysdesc System Monitor Synthesis Design- Flow CDFG of Micro-Tasks EMF-based Intermediate Model of the System SM Generation EMF-based RTL-Model for System Monitor Code-Generation Tool SM.vhd Figure 1.6: Complete system-level design-flow

Synthèse, caractérisation et polymérisation par ouverture de cycle ...
Emission gamma de haute énergie dans les systèmes binaires ...
UN SEMINAIRE INTERNATIONAL DE HAUT NIVEAU ... - EPSA 2011
Analyse et synthèse de sons de piano par modèles physiques et de ...
Test et Consommation des Circuits N é i P blé ti t Numériques ...
Martin Teichmann Atomes de lithium-6 ultra froids dans la ... - TEL