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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 30 Introduction 1.4 Contributions The main contributions of this work can be described as under: � We provide an integrated design-flow for micro-task-based WSN node controller synthesis. In this flow, the behavior of each micro-task is specified in C and is mapped to an application specific micro-architecture using a modified version of a retargetable compiler infrastructure. � We also show that the power-gating scheme happens to have very short switchingtime delays, in the orders of a few hundred of nano seconds for average-size hardware micro-task designs. This improves the wake-up response time by at least 50 % when compared to low-power MCUs such as the MSP430. � We also provide a DSL that can be used to specify the system-level execution model of a WSN node that in turn generates the hardware description for the system monitor (SM) that is used to control the activation and deactivation of the power-gated hardware micro-tasks. � Our approach provides power savings of one to two orders of magnitude in dynamic power when compared to the power dissipation of currently available lowpower MCU-based solutions. � We also use this flow to perform design space exploration by exploring the tradeoffs in power/area that can be obtained by modifying the bitwidth of the generated hardware micro-tasks. We compare the obtained results to those achieved by using an off-the-shelf low-power MCU such as the MSP430. � We performed realistic case-study of a WSN application that serves as an experimental validation that the approach is conceivable for real-life WSN systems. 1.5 Thesis organization The thesis is organized in 7 chapters. Chapter 2 presents the related work about power optimization of WSN node architecture. It starts by briefly covering the basics of WSN systems. It then describes the generic components of a WSN node and their contribution to the node’s power budget. Chapter 2 covers the commercially available WSN node architectures and provides a short survey of their features and design parameters. It provides a summary of power reduction techniques developed at different design levels of a WSN node such as micro-architectural level and VLSI circuit level. Since our design-flow for micro-task generation is based on a hybrid of High-Level Synthesis (HLS) and ASIP design methodologies, Chapter 3 provides a survey of the existing work done in both of these domains. It starts with generic HLS design methodology and covers the existing tools for HLS. Similarly, it also discusses the ASIP designflows and existing tools.

tel-00553143, version 1 - 6 Jan 2011 Thesis organization 31 Chapter 4 thoroughly describes our proposed design-flow for hardware micro-task synthesis. It starts by explaining the notion of a hardware micro-task, the basic building block of our proposed approach. It discusses its potential power benefits and generic architecture. It then concludes with a comprehensive description of our proposed microtask synthesis design-flow and a small experimental demonstration. Chapter 5 covers the second half of our design tool, LoMiTa, that is the development of a system-level execution model and design-flow for the hardware SM synthesis. It starts by a brief introduction to existing execution paradigms in embedded systems and why event-driven approach is more suitable for WSN systems. It then covers the systemlevel view of the computation and control part of a WSN node based on our approach. It then adds a comprehensive survey of existing WSN-specific OS that are used for task- and power-management in conventional WSN nodes. Chapter 5 summarizes the features of our proposed system-level execution model afterward and finally concludes with the details of the System Monitor (SM) synthesis design-flow and a simple example demonstrating the power benefit and area overhead of a hardware SM. Chapter 6 consists of the experimental setup and the results that we have achieved. It starts by describing the effects of using power-gating technique in our system and achieved improvement in wake-up response time. It then covers the dynamic and static power reductions achieved by our approach as compared to the currently available lowpower MCUs in the light of a case study WSN application. Additionally, it provides the findings based on the design space exploration that we performed by varying the sizes and bitwidths of the micro-task components and summarizes an optimal option. Chapter 6 also provides the result for the power consumption of the SM controlling the micro-tasks of our case-study example and compares it with an MCU-based software solution. It concludes with the expression of overall energy gain for a complete timeperiod of a micro-task activation. Chapter 7 concludes the work done in the thesis along with the international publications extracted from this work and draws some future research directions.

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