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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 40 WSN node architectures and low-power microcontrollers to embedded web servers, which come equipped with a wide range of interconnection possibilities such as Bluetooth, a low-power radio mode, as well as connections following I 2 C or CAN (Controller Area Network) protocols are also possible. Similarly, the Hydrowatch platform is also built on the MSP430F1611-core [39]. Apart from these academic research prototypes, there are already a couple of sensornode-type devices commercially available, including appropriate housing, certification, and so on. Some of the companies designing commercial WSN nodes include Millenial 2 and Ember 3 . As our current research work is focused on the power/energy optimization of the computation and control subsystem of a sensor node, in the next section of this chapter we will discuss the evolution of low-power solutions for the control subsystem and present some related work about the low-power microcontrollers and their power optimization techniques. 2.5 Emergence of low-power microcontrollers Microcontrollers that are used in several wireless sensor node prototypes include the ATMega series by Atmel Corporation or the MSP430 by Texas Instrument. In older prototypes, the Intel StrongArm SA1100 processors have also been used, but it is no longer considered as a practical option (it is included here for the sake of comparison and completeness). These MCUs have several common characteristics such as a simple datapath (8/16-bit wide), a reduced number of instructions, and several power saving modes to have lower power consumption of the system. The power saving modes adapted in low-power MCUs use VLSI circuit level techniques to reduce the power consumption of the system. Hence, in the following section, we investigate some of the most noticeable power optimization techniques adapted at VLSI circuit level to engineer an energy-efficient design. Some of the key figures about the power consumption of these low-power MCUs are presented afterward. 2.5.1 Power optimization at VLSI circuit level In the last decade, there have been a large number of research results dealing with power optimization in VLSI circuits (see [28, 108] for surveys on the topic). Power dissipation in VLSI circuits can be divided into two categories: � Dynamic power: This power dissipation has two sources, (i) capacitance switching (i.e. stage changes) that occurs while the circuit is operating and (ii) short-circuit current passing through the gates. � Static power: It is caused by leakage current between power supply and ground of the circuit. 2 http://www.millenial.net 3 http://www.ember.com

tel-00553143, version 1 - 6 Jan 2011 Emergence of low-power microcontrollers 41 ISC VDD Figure 2.3: Currents contributing to various power consumptions in CMOS circuits. The total power dissipation of a Complementary Metal-Oxide-Semiconductor (CMOS) gate i is the sum of dynamic power and static power and can be expressed as ILeak GND ISW CLoad Ptotal = 1 2 CifclkαiV 2 DD + VDDIsci + VDDIleaki (2.1) where VDD is the supply voltage, Ci the output capacitance, αi the activity at the output of gate i, fclk the switching frequency and, Isci and Ileaki the short-circuit and leakage current of gate i respectively. Figure 2.3 shows the currents that contribute to the dynamic and static power in a CMOS circuit, ISW is the current that flows while charging and discharging of the output capacitance (stage change), ISC is the shortcircuit current flowing when both the NMOS and PMOS transistors conduct for a short duration at input transition whereas ILeak is the leakage current flowing through the gate even when it is not operating. When a CMOS device is active, its power is usually largely dominated by dynamic power, and becomes roughly proportional to clock frequency. However, in the context of WSN, things are sightly different as the node remains inactive for long periods (MCU duty cycle lower than 1%), and the contribution of static power also becomes significant and can not be ignored. Moreover, as process technology passes 65 nm and continues toward 45 nm and below, where the operating voltages are lower, and the switching thresholds roll off more rapidly, static power dissipation is expected to exceed dynamic power dissipation and become the dominant contributor to the total power of a device. Therefore, static power minimization must be considered as an integral part of the power reduction strategy. Figure 2.4 points out this ever-increasing share of static power dissipation in overall system power [125]. There are several approaches to reduce the power dissipation in a CMOS circuit, some of them are summarized in the following paragraphs.

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