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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 42 WSN node architectures and low-power microcontrollers Power (W) 300 250 200 150 100 50 0 Leakage Power Dynamic Power Leakage Power Vs. Dynamic Power Technology Dynamic Power Leakage Power 250 40 5 180 45 15 130 65 25 90 80 60 70 100 140 250 180 130 Process Technology (nm) 90 70 Figure 2.4: Scaling of static and dynamic power consumption with the advancements of process technology. 2.5.1.1 Clock gating Clock is considered as a major contributor to the power dissipation, as it is the signal with the greatest switching activity. In addition, the clock signal tends to be highly loaded as it has a high fan-out and corresponding high switching capacitance. To distribute the clock and control the clock skew, one needs to construct a clock network (often a “clock-tree”) with clock buffers. All of this adds to the capacitance of the clock network. Recent studies (e.g. [143]) indicate that the clock signals in digital systems consume a large percentage (15% to 45%) of the system power. In order to reduce the unnecessary power consumption caused due to clock-trees, Clock gating is used. Clock gating consists in gating the clock signals that drive inactive portions of the circuit. The purpose is to minimize the switching activity on flip-flops and clock distribution lines. For instance, large VLSI circuits such as processors contain register files, arithmetic units and control logic. All the registers in a register file are generally not accessed in each clock cycle. If simple conditions that determine the inaction of particular registers are determined, then power reduction can be obtained by gating the clocks of these registers [19]. When these conditions are satisfied, the switching activity within the register file is reduced to negligible levels. Figure 2.5 shows one of the typical gated-clock design styles. The “enable-logic” consists of combinational elements and determines whether a clock signal should be supplied to the registers or not. If the output of the enable-logic is equal to zero, clock signal is not propagated to the clock-inputs of the registers. An AND-gate or an OR-gate which satisfies following two conditions is called “gated buffer”. (i) The output of the gate is connected to the clock-input of the registers. (ii) One input of

tel-00553143, version 1 - 6 Jan 2011 Emergence of low-power microcontrollers 43 Data F/F NCLK CLOCK Root Driver Enable Logic De-glitch Latch Gated Buffer GCLK NCLK Figure 2.5: Example of gated-clock design. Registers Registers the gate is an enable signal coming from the “enable-logic”, while the other input is the original clock signal. On the contrary, a buffer without gating function is called “normal buffer”. The “de-glitch latch” is inserted between the enable-logic and the gated buffer to eliminate glitches which occur in the enable-logic and can result in un-expected behavior of the circuit. A clock signal used in the gated-clock technique is called “gated clock signal” (say GCLK), while the non-gated clock signal is called “normal clock signal” (say NCLK). Kitahara et al. [75] suggested an automated layout design technique for the clockgated design and proposed tools to minimize the gated-clock net skew and to maintain timing constraints for enable-logic parts. They proved that about 30% power reduction could be achieved for the whole design by clock-gating using their techniques. Wu et al. [143] used another technique that is based on quaternary representation for behaviors of signals. They presented a method of finding a gated clock signal instead of a normal clock signal using Karnaugh maps, by checking quaternary value of each flipflop in a circuit. Using extended Boolean functions, the authors found the enable logic for clock signals to be connected to the actual circuit and showed that the new clock-gated design reduces the power dissipation by 22%. Garrett et al. [43] looked at the impact of the physical design on a hierarchical gated clock-tree and its power dissipation. They found that there is an inherent pitfall in implementing gating groups for hierarchical gated-clock distribution because the groups are typically developed at the logic level with no information of the physical layout of the clock-tree. Depending on the distribution of underlying sinks, maintaining gating groups can cause a wiring overhead that is potentially greater than the savings due to reduced switching. Hence, their suggested algorithms took both the logical and physical aspects of the design and generated a more power-optimized solution that results in a 24% more power-saving in clock-trees.

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