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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 44 WSN node architectures and low-power microcontrollers 2.5.1.2 Voltage scaling Voltage scaling is one of the most powerful and frequently-used tools to reduce the dynamic power dissipation. A quadratic improvement can be easily achieved through lowering the supply voltage (Equation 2.1). Although this technique is very effective, the speed of the circuits is degraded as the propagation delay increases with the decrease in supply voltage. Equation 2.2 shows the proportional relation between supply voltage VDD and propagation delay tpd. tpd ∝ VDD (VDD − Vth) α (2.2) where α is a factor depending on the carrier velocity saturation and is about 1.3 in advanced MOSFETs [67]. A derivative of this approach is to use multiple voltages in a system for different parts of the circuit depending upon their critical path delays. For instance, microprocessors with dual supply voltage scaling technique have the dramatic effect on power consumption reduction. The technique can significantly reduce dissipated power without degrading speed by using lower supply voltage along non-critical delay paths and higher supply voltage along critical delay paths [88]. The main problems of using dual supply voltage scaling in CMOS circuits are the increased leakage current in the high voltage gates when they are driven by low voltage gates, and the routing of two power-supply grids. One solution is to use an additional circuit of level converter, but it introduces area and energy overhead. On the other hand, some researchers proposed Clustered Voltage Scaling (CVS), where no low voltage gate will drive a high voltage gate [139]. However, both of these techniques introduce additional constraints to the dual supply voltage scaling process, and reduce the overall energy savings. In contrast to the above-mentioned techniques that implement the voltage scaling at circuit level, there have been several other approaches that proposed to implement multiple supply voltages at other levels of design-cycle as well. For instance, Chang et al. [20] presented a dynamic programming technique for solving the multiple supply voltage scheduling problem in both non-pipelined and functionally pipelined datapaths. The scheduling problem was concerned to the assignment of a supply voltage level (selected from a fixed and known number of voltage levels) to each operation in a “Data Flow Graph (DFG)” so as to minimize the average energy consumption for given computation-time or throughput constraint or both of them. They showed that using three supply voltage levels on a number of standard benchmarks, an average energy saving of up to 40% can be obtained compared to using a single supply voltage level. 2.5.1.3 Transistor sizing Transistor sizing in a combinational circuit significantly impacts the circuit delay and power dissipation. If the transistors in a given gate are increased in size, the delay of the gate decreases, however, it increases the delay and the load capacitance of the fan-in gates. A typical approach to find the optimum transistor size, given a delay constraint, is to compute the slack at each gate in the circuit, where the slack of a

tel-00553143, version 1 - 6 Jan 2011 Emergence of low-power microcontrollers 45 VG VVDD Block A VDD VVDD VVDD Block B Block C Figure 2.6: The use power gating to reduce the overall circuit power. gate corresponds to how much the gate can be slowed down without affecting the critical delay of the circuit. Sub-circuits with slacks greater than zero are processed for transistor-size reduction until the slack becomes zero, or the transistors reach the minimum size. A similar approach is used in the work by Tan et al. [127]. However, for a given delay-constraint finding an appropriate sizing of transistors that minimizes power dissipation is a computationally difficult problem. 2.5.1.4 Power gating One important issue with all of the above-mentioned techniques so-far is that they work for dynamic power reduction of a circuit and are poorly suited to WSN nodes as they significantly increase the total silicon area by adding extra components (e.g. a level converter in case of dual voltage scaling, gated buffer and enable-logic for clock gating), and therefore have a negative impact on static power dissipation. However, one exception is power gating, that consists in turning-off the power supply of inactive circuit components [12, 87] which helps reducing both dynamic and static power. It is thus a very efficient optimization for devices in which components remain idle for long time periods. The technique consists in adding a sleep transistor between the actual VDD (power supply) rail and the component’s VDD, thus creating a virtual supply voltage called VV DD as illustrated in Figure 2.6. Similarly a sleep transistor between the actual GND (ground) rail and the component’s GND can also be added, creating a virtual ground called VGND. The sleep transistor, in first case, allows the supply voltage of the block to be cut off to dramatically reduce leakage currents. In practice, Dual VT CMOS or Multi-Threshold CMOS (MTCMOS) techniques are used for power gating implementation [95, 69]. Research work is also being done on the sleep transistor sizing to further reduce the leakage power caused by the sleep transistor insertion [22]. Since one centralized sleep transistor design suffers from large interconnect resistances between distant blocks, such resistance has to be compensated by extra large sleep transistor area that could result in extra load capacitance and delay for driving logic. Hence, two approaches have been proposed to divide the overall circuit into seg

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