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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 46 WSN node architectures and low-power microcontrollers ments and apply several sleep transistors to achieve a more-efficient design. Anis et al [7] proposed a cluster-based design structure, where each cluster, consisting of several gates, is accommodated by a sleep transistor separately. The size of the sleep transistor is determined by the current of the cluster. Their approach achieved a 90% reduction in static power consumption as well as 15% reduction in dynamic power consumption. Long et al. [87] proposed another approach that uses a distributed network of sleep transistors. This approach is better than the cluster-based approach in terms of sleep transistor area and circuit performance and obtains sleep transistor networks that are 70% more area-efficient than the cluster-based networks. Power gating has already been used in the context of high performance CPUs [59], and FSM implementations [113] where parts of the design are switched on/off according to their activity. The approach helps in reducing the static power dissipation for FPUs of a high-end CPU by up to 28% at the price of a performance loss of 2%, for FSMs the average reported power reduction was also 28%. In the context of WSN, where nodes remain idle most of the time, such a technique has obvious advantages, and is therefore intensively used for implementing the low power modes of typical node MCUs. Most of the above-mentioned VLSI power-optimization techniques have been deployed in ultra low-power microcontrollers targeted toward low-power embedded system applications. A brief overview of these Commercially-Off-The-Shelf (COTS) microcontrollers that are currently being used in most of the existing WSN nodes is presented in the following section. 2.5.2 Commercial low-power MCUs In recent years, due to rapid evolution of embedded systems, several low-power microcontrollers have evolved. However, since these MCUs are designed for low-power operation across a wide range of embedded system application settings, they might not be very well-suited to the event-driven behavior of WSN nodes as they are based on a general purpose, monolithic compute engine. In this section we present the features of some of the most notable COTS microcontrollers being used by the WSN community for WSN node development. Texas Instruments MSP430 series The MSP430 family features a wider range of low-power 16-bit MCUs. For instance, the MSP430F1611 requires 500 µA (@ 1 MHz and 3.0V) whereas an updated series, designed for WSN nodes, the MSP430F21x2 consumes approximately 250 µA (@ 1 MHz and 2.2V) [129]. There are four sleep modes in total. The deepest sleep mode, LPM4, consumes only 0.1 µW, but the controller can only be woken up by external interrupts in this mode. The MSP430 has a maximum operating frequency of 16 MHz. Atmel ATMega series Atmel Corporation has also developed a wide range of 8-bit MCUs that are used by a variety of embedded system applications. In particular, for WSN node platforms,

tel-00553143, version 1 - 6 Jan 2011 Emergence of low-power microcontrollers 47 Figure 2.7: Architecture of CoolRISC 88 processor (extracted from the work of Piguet et al. [109]). ATmega128L and ATmega103L have been used [9, 8]. ATmega128L consumes an average 8 mA (@ 8 MHz and 3.0V) whereas the older version ATmega103L, with an operating frequency of 4 MHz max., consumes approximately 5.5 mA (@ 4 MHz and 3.0V). The ATmega128L has a maximum operating frequency of 8 MHz. EM Microelectronic CoolRISC EM Microelectronic has also come-up with an ultra low-power solution for 8-bit microcontroller called CoolRISC [33]. An EM6812 (based on CoolRISC) consumes approximately 120 µA (@ 1 MHz and 3.0V) [33], whereas it has a maximum operating frequency of 5 MHz (2.5 MIPS). Historically, original CoolRISC was a low-power processor designed to achieve a lower value of Clock per Instruction (CPI) to reduce the power consumption by working in lower frequency range. At that time, CoolRISC 88 achieved a CP I = 1 by providing 10 MIPS performance and an operating frequency in the range of 1 to 10 MHz [109]. The legacy CoolRISC 88 having a register file of 8 registers is shown in Figure 2.7 (extracted from the work by Piguet et al. [109]). It was built in 1 µm process technology that resulted in a lower power consumption. It consumed around 60 µA at 3.0 V while working at 1 MHz. NXP LPC111x NXP Semiconductors have recently launched a series of MCUs, LPC111x that are based on ARM Cortex-M0 [100]. These are 32-bit MCU cores with an average of 3.0 mA

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