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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 48 WSN node architectures and low-power microcontrollers WSN MCU Normalized Power Actual Power ATmega103L 66 mW (@ 16 MHz) 5.5 mA (@ 4 MHz, 3.0V) ATmega128L 48 mW (@ 16 MHz) 8 mA (@ 8 MHz, 3.0V) MSP430F1611 24 mW (@ 16 MHz) 500 µA (@ 1 MHz, 3.0V) MSP430F21x2 8.8 mW (@ 16 MHz) 250 µA (@ 1 MHz, 2.2V) EM-6812 (CoolRISC) 5.76 mW (@ 16 MHz) 120 µA (@ 1 MHz, 3.0V) LPC111x (ARM Cortex-M0) 13.2 mW (@ 16 MHz) 3.0 mA (@ 12 MHz, 3.3V) StrongArm SA-1100 40 mW (@ 16 MHz) 400 mA (@ 160 MHz, 2.0V) Table 2.2: Actual and normalized power consumption for various low-power MCUs. (@ 12 MHz, 3.3V) that can run up to an operating frequency of 50 MHz. LPC111x consumes around 6 µA (@ 3.3V) in deep-sleep mode without any active clock. Intel StrongArm SA-1100 The Intel StrongARM [66] provides three power modes: (i) In normal mode, all parts of the processor are fully powered. Power consumption is up to 400 mW (@ 160 MHz, 2.0V). (ii) In idle mode, clocks to the CPU are stopped while clocks to peripherals are active. Any interrupt will cause return to normal mode. The power consumption is up to 100 mW. (iii) In sleep mode, only the real-time clock remains active. Wake-up occurs after a timer interrupt and takes up to 160 ms and the power consumption is up to 50 µW. Table 2.2 summarizes power consumptions of all the above MCUs at a normalized operating frequency of 16 MHz. 2.5.3 WSN-specific sub-threshold controllers Apart from the general-purpose COTS processors, there are several WSN-specific controller implementations that have been proposed by the research community. These controllers try to exploit the WSN-specific characteristics such as event-centric behavior and asynchronous communication to achieve an extremely low-power consumption as well as a considerably lower energy per instruction. In this section, we will briefly discuss some of the most significant WSN-specific processors present in the literature. 2.5.3.1 SNAP/LE processor The SNAP/LE, proposed by Ekanayake et al. is an ultra low-power asynchronous processor [31]. The processor instruction set is optimized for WSN applications, with support for event scheduling, pseudo-random number generation, bit-field operations, and radio/sensor interfaces. SNAP/LE has a hardware event queue and event coprocessors, which allow the processor to avoid the overhead of operating system software (such as task schedulers and external interrupt servicing), while still providing a straightforward programming interface to the designer. Figure 2.8 shows the basic micro-architecture of SNAP/LE. The timer coprocessor is used for timing synchronization and generates

tel-00553143, version 1 - 6 Jan 2011 Emergence of low-power microcontrollers 49 IMEM DMEM Fetch Decode busses execution units event queue Timer Coproc. Register File Message Coproc. Figure 2.8: Microarchitecture of the SNAP/LE processor showing major components. internal time-outs whereas message coprocessor is used for message exchange with the RF-transceiver. The decode stage in Figure 2.8 is a normal stage whereas instructionfetch along with the event queue forms a FIFO-based hardware task scheduler. The instruction-fetch waits for an event in the event queue and uses this event as an index to access the SNAP/LE’s “event handler table” to address a proper event handler. It then starts fetching the instructions concerning the relative event handler until a “done” instruction is encountered. The instruction-fetch then checks the event queue for a possible next event. The dots (in the figure) correspond to the instruction tokens being processed by the SNAP/LE processor core. Running at its highest core voltage of 1.8 V, the SNAP/LE core consumes under 300 pJ/instruction while working at 600 mV it consumes 75 pJ/instruction with several instructions as low as 25 pJ/instruction. The SNAP/LE processor is implemented in 180 nm process technology. 2.5.3.2 Accelerator-based WSN processor Hempstead et al. [53] proposed a processor design that is compliant with the acceleratorbased computing paradigm, including hardware accelerators for the network layer (routing) and application layer (data filtering). Moreover, the architecture can disable these accelerators via VDD-gating to minimize leakage current during the long idle periods common to WSN applications. They implemented a system architecture for WSN nodes in 130 nm CMOS technology that operates at 550 mV and 12.5 MHz. Figure 2.9 shows the general architecture of this processor. There is an event-handler implemented in hardware that performs the regular event management, then there is a general purpose MCU for irregular event management and finally there are several accelerators for application and network level tasks such as message routing and data filtering etc. Since the commonly used metric of energy-per-instruction can not be easily msg fifos

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