Views
5 years ago

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 50 WSN node architectures and low-power microcontrollers Tester I/O Interrupt Controller Event Processor Interrupt Processing/ Power Management (Regular Events) SRAM (2 x 2KB) ADDRESS Bus Signal Power Enable Lines POWER CONTROL DATA INTERRUPT µController General Processing (Irregular Events) Timer Subsystem Programmable Data Filter Message Processor Figure 2.9: System architecture of the accelerator-based WSN processor. applied to accelerator-based systems, the authors introduced the concept of“energy-pertask”. They defined a task as a collection of dependent computations that are executed periodically. They presented measurements of a task similar in nature to a volcano monitoring application. This task took 131 cycles to execute and consumed 678.9 pJ at 550 mV and 12.5 MHz. An equivalent routine written for the Mica2 mote required 1532 instructions. Using this information, they computed the energy per equivalent instruction as 0.44 pJ/instruction for accelerator-based mode while 3.4 pJ/instruction in general purpose mode for their processor. Even though their idea of benefiting from hardware acceleration and power-gating is similar to ours, they design all of their accelerators manually and work in subthreshold voltage domain that is prone to inconsistencies due to thermal and process variations. On the other hand, we propose a complete automated design-flow for the generation of specialized hardware blocks and our designs work at above-threshold voltage domain to avoid complications. Moreover, the authors did not provide any details about the general purpose microcontroller present in their system and its Instruction-Set Architecture (ISA), hence it is difficult to judge their claims about an energy efficiency of 3.4 pJ/instruction that is 20x times better than an asynchronous processor (SNAP/LE) performing nearly the same job.

tel-00553143, version 1 - 6 Jan 2011 Emergence of low-power microcontrollers 51 JTAG test port clock oscillator voltage converter interface (SPI, I²C, GPIO) serial (console) power manager Power Ctrl. Bus neighbor location 64kB Mem 256B Reg. File dw8051 µC (apps & network) 1kB packet queues data link layer (dll) baseband OOK TX/RX ADC Charm DSP Chip External Radio Figure 2.10: Block diagram of the Charm protocol processor. 2.5.3.3 Charm processor The Charm processor [123] developed at the University of California at Berkeley is a protocol processor implemented in 130 nm technology and implements a protocol stack tailored for WSN applications. Its subsystems follow the OSI model and include the application, network, data link, and digital baseband portion of the physical layers. As shown in Figure 2.10, the processor chip contains a synthesized 8051-compatible microcontroller with 64 kilo-Byte of program/data RAM, two 1 kilo-Byte packet queues, a custom data-link layer (DLL), a neighborhood management subsystem, digital portion of a custom baseband, a location computation subsystem, and several external interfaces. Charm processor uses a unique approach that, instead of using VDD-gating, reduces the power rail voltage to a “Data Retention Voltage (DRV)” that maintains the state in the logic, while still reducing leakage current. Hence, the system has a trade-off of data retention for a relatively higher leakage power dissipation. It works at 1.03 V and consumes 96 pJ/instruction [53]. 2.5.3.4 Phoenix processor Seaok et al. developed the Phoenix processor (shown in Figure 2.11), that works at 500 mV and consumes as low as 2.8 pJ/cycle [122]. The Phoenix processor exploits both the voltage scaling as well as a comprehensive sleep transistor technology to obtain an ultra low-power processor design. The CPU works on an even-driven paradigm and the authors claim to intentionally use an older low-leakage 0.18 µm process technology to further reduce the static power consumption. However, the authors did not provide any information about the CPU being used or its ISA. Similarly, no information about the clock-cycles taken by the CPU instructions is provided. Hence, it impossible to interpret their energy efficiency metric “energy/cycle” to normal metric such as “energy/instruction”.

Les bus à haut niveau de service
Synthèse, caractérisation et polymérisation par ouverture de cycle ...
CONVENTION INDIVIDUELLE ATHLETES DE HAUT NIVEAU saison 2014-2015
Analyse et synthèse de sons de piano par modèles physiques et de ...
UN SEMINAIRE INTERNATIONAL DE HAUT NIVEAU ... - EPSA 2011
Emission gamma de haute énergie dans les systèmes binaires ...
[pastel-00600598, v1] Synthèse de composés ... - Chimie ParisTech
Synthèse, caractérisation et intérêt biomédical de (glyco ...
Martin Teichmann Atomes de lithium-6 ultra froids dans la ... - TEL
Test et Consommation des Circuits N é i P blé ti t Numériques ...
Etude des systèmes RFID opérants en rétrodiffusion modulée ultra ...
Du sillage des insectes aux gaz de Fermi ultra-froids: dynamique ...
Analyse tth, H EN WW avec ATLAS au LHC et étude des électrons à ...
Computer: PicoRadio Supports Ad Hoc Ultra-Low Power Wireless ...
Electroproduction de pions neutres dans le Hall A au Jefferson ...