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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 52 WSN node architectures and low-power microcontrollers 2.5.3.5 BlueDot 64x10 (IMEM) 128x10 (IROM) Clock Generator System Bus CPU Compress/ Decompress Timer Temp. Sensor --- 52x40 (DMEM) I/O Power Management --- Partially Gated Not Gated Power Gated Figure 2.11: Block diagram of the Phoenix processor. Very recently, Raval et al. [119] have proposed BlueDot, a low-power TinyOS-tuned processor platform for WSN nodes implemented in 130 nm process technology. The BlueDot is compatible with Atmel ATmega128L series processors and an application code written for ATmega128L-centric nodes can run on BlueDot-based nodes as well. A BlueDot-based platform can also benefit from several hardware-accelerators that can be used to implement frequently used application/control codes such as communication with RF-transceiver through SPI-bus. The BlueDot platform, with an optimized processor (having WSN-specific Instruction-set Architecture (ISA)) and RF-accelerator, consumes 26 pJ/instruction on average. It consumes around 48% less energy than the baseline ATmega128L-equivalent processor when executing the same WSN application suite that is around 1.5 mJ on average. However, the authors did not provide the area and power usage comparison w.r.t. the base-line ATmega128L processor. It is quite possible that the overall area of the node as well as static power is increased by adding the hardware accelerators along with the base-line processor that could result in a less power-efficient design in standby mode. 2.5.4 Conclusion Though all of these WSN-specific processors show impressive energy efficiency in terms of Joules/instruction as compared to general purpose COTS processors mentioned ear

tel-00553143, version 1 - 6 Jan 2011 Emergence of low-power microcontrollers 53 lier, they also suffer from their inherent weaknesses. For instance, subthreshold logic is highly susceptible to temperature and process variations. In addition, due to the low voltage swing, noise arising from other on-chip components could be an issue for commercial WSN applications. As far as asynchronous processors are concerned, it can be difficult to integrate asynchronous logic into conventional, commercial synchronous design flows for low-cost System-on-Chip (SoC) solutions. For this reason, asynchronous logic is considered unattractive for many applications. Moreover, most of these processors are manually designed and optimized and no automatic design and programming tool exists for them. Due to these inherent problems of subthreshold and asynchronous WSN-specific processors and a very high power consumption of general purpose COTS processors, we focused on the development of a novel approach that is based on hardware specialization and power gating that is built upon a hybrid concept of High-Level Synthesis (HLS) and retargetable compilation for ASIP (Application Specific Instruction-Set Processor). The next chapter presents a comprehensive state-of-the-art about HLS and ASIP design tools.

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