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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 54 WSN node architectures and low-power microcontrollers

tel-00553143, version 1 - 6 Jan 2011 Chapter 3 High-level synthesis and application specific processor design As discussed in Section 1.3.3, our work consists of two distinct design-flows. The first one takes the overall system-level behavioral description of application (using a Domain Specific Language (DSL)) as an input and generates an RTL VHDL description of the global system monitor. On the other hand, the second design-flow takes the C-specification of the tasks present in the application task graph and generates the specialized hardware blocks, called hardware micro-tasks, for each of them. As our design-flow for hardware micro-task generation is a hybrid of High-Level Synthesis (HLS) and Application Specific Instruction-set Processor (ASIP) design methodologies, we present, in this chapter, the existing work done in the domain of HLS and ASIP design. The chapter starts with the generic methodology for HLS and discusses the existing algorithms as well as academic and commercial tools available for HLS. In a similar fashion, it then presents the generic methodologies for ASIP design and corresponding algorithms. The chapter finally concludes with a discussion on some of the existing academic and commercial tools for ASIP design. 3.1 High-Level Synthesis (HLS) Rapid advancements in silicon technology and the increasing complexity of applications in recent decades have forced design methodologies and tools to move up to higher abstraction levels. Raising the abstraction levels and accelerating automation of both synthesis and verification tools have been major key factors in the evolution of design process. Moreover, the use of high-level models has enabled system-designers, rather than circuit-designers, to be productive and to match the industry trends which is delivering an increasingly large number of integrated systems in place of integrated circuits. The HLS design relates to leaving the implementation details to the design algo- 55

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