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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 56 High-level synthesis and application specific processor design rithms and tools, and thus represents an ambitious attempt by the research community to provide capabilities for“algorithms to gates”for a period of almost three decades [48]. HLS takes as its input a behavioral description in the form of a high-level language and generates an RTL circuit [85]. In the next section, we summarize the generic design-flow for HLS found in the literature. 3.1.1 Generic HLS design-flow Coussy et al. [24] presented a generic design-flow that is shared by most of the HLS tools. This design-flow consists of seven major steps that are highlighted in Figure 3.1. We briefly discuss some of these design steps: � Compilation: HLS always begins with the compilation of the functional specification. This first step transforms the input description into a formal representation. This step includes several code optimizations such as dead-code elimination, constant folding and loop transformations etc. and generates an intermediate specification that can be in the form of a CDFG. � Allocation: Allocation defines the type and the number of hardware resources (e.g. functional units, storage, or connectivity components) needed to satisfy the design constraints. These components are selected from the RTL component library. The library must also include component characteristics (such as area, delay, and power) and its metrics to be used by other synthesis tasks. � Scheduling: All operations required in the specification model must be scheduled into cycles. Depending on the functional component to which the operation is mapped, the operation can be scheduled within one (or several) clock cycle(s). The operations can be scheduled in parallel or sequential fashion depending upon the data dependencies between them and if there are sufficient resources available at a given time. � Binding: This step binds the variables carrying a life-time of several clock cycles to storage resources. Similarly, the operations are bound to the functional units that are optimally selected for given design constraints. � Generation: Once decisions have been made in the preceding tasks of allocation, scheduling, and binding, the goal of the RTL architecture generation step is to apply all the design decisions made and generate an RTL model of the synthesized design. Now we briefly discuss the algorithms that have been mostly used in the existing work during different steps of the HLS design-flow such as operation scheduling, resource allocation and binding.

tel-00553143, version 1 - 6 Jan 2011 High-Level Synthesis (HLS) 57 3.1.2 Scheduling Library Specification Compilation Intermediate Representation Allocation Scheduling Binding Generation RTL Architecture Logic Synthesis Figure 3.1: Design methodology for high level synthesis (HLS) Operation scheduling consists of assigning each operation at behavioral level (e.g. DFG) to a control step (also called a C-step [106]). Generally speaking, scheduling determines the cost-speed trade-off of a hardware design generated through HLS. If the target design is subject to a timing/speed constraint, the scheduling algorithms will try to meet the timing constraint through operation parallelization and an optimum algorithm will provide a solution with the minimum hardware resources under the given timing constraint. On the other hand, if there is a limit on the cost (area or resources) of the target design, the scheduling algorithms will serialize the operations to meet the resource constraint. In this case, the optimum solution will be the one that reduces the overall execution time while keeping the resource constraint into consideration. Scheduling, without resource constraints is simple as it consists in a topological sorting of the operations and can be solved in polynomial time for an optimal solution. Two of the algorithms to solve such scheduling are discussed in the following paragraphs. 3.1.2.1 ASAP scheduling The simplest scheduling technique is As Soon As Possible (ASAP) scheduling where the operations in the DFG are scheduled step-by-step from the first control step to the last. An operation is called ready operation if all of its predecessors are scheduled. This procedure repeatedly schedules ready operations to the next control step until all the ...

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