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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 62 High-level synthesis and application specific processor design Graph coloring algorithm: Graph coloring algorithm is an assignment of labels, traditionally called colors, to elements of a graph subject to certain constraints. Formally speaking, the situation is described by a graph G = (V, E) with vertex-set V and edge-set E formed by all pairs of incompatible elements. Partitioning of V into k subsets is equivalent to coloring the vertices of G with k colors. In simpler form, it is a way of coloring the vertices of a graph such that no two adjacent vertices share the same color; this is called a vertex coloring. In register allocation, an interference graph is constructed, where vertices are symbolic registers and an edge connects two nodes if they are needed at the same time (i.e. they are alive at the same time and cannot be assigned to the same physical register). If the graph can be colored with k colors then the variables can be stored in k physical registers. Both graph coloring and register allocation (except for some special cases, such as expression trees) are NP-Complete problems. Fortunately, there exist several methods such as greedy algorithm, breadth-first search, brute-force search to solve the problem of vertex coloring with a linear-time approximation and they could yield to good results but without ensuring optimality. After discussing the existing design methodology and corresponding algorithms for each stage of the HLS design-flow, we present some academic as well as commercial tools that are based on these principles and are being used by the HLS research community. 3.2 Power-aware HLS tools HLS tools have been developed for targeting different design constraints such as lowpower, low silicon foot-print, FPGA resource optimization, wordlength optimization for Digital Signal Processing (DSP) applications etc. Since our work targets a lower power consumption of the generated hardware, we will mainly focus on the power-aware HLS tools. 3.2.1 SCALP Ragunathan et al. [117] proposed SCALP, an iterative-improvement-based low-power datapath synthesis tool that targets data-oriented application domain. It adopts a heuristic based approach for solving different HLS tasks such as scheduling, resource binding and resource sharing etc. It also offers various optimizations such as compilerlevel transformations, appropriate clock and supply-voltage selection for a power-efficient design, retiming, datapath merging as well as slower functional-unit selection (if permitted by the timing constraint) to avoid excessive switching capacitance and reduce the dynamic power of the resultant hardware. One of the main problems with SCALP, in our point of view, is that it is targeted toward data-dominated applications and its feasibility toward control-oriented applications (such as WSN) is not shown. It also generates an interconnect-unaware solution that does not consider the power dissipated by the interconnects and thus provides a relatively less power-efficient solution.

tel-00553143, version 1 - 6 Jan 2011 Power-aware HLS tools 63 3.2.2 Interconnect-Aware Power Optimized (IAPO) approach Zhong et al. [85] provided an improvement over some HLS tools by taking into consideration of the power consumed by interconnect. They added a notion of interconnectaware resource-binding in SCALP. They considered multiplexer-based interconnects in their system and provided two methodologies for improved interconnect-bindings: � Neighborhood-aware binding: the nodes in a CDFG that exchange data with each other are mapped to the datapath units (DPUs) such that they are physically placed closer to each other during floor-planning to reduce the communication cost. � Communication-sensitive binding: the authors added a weighted communication gain to the cost gain for DPU-sharing moves. It is based on the unit-length switched capacitance of the data exchange between the corresponding two DPUs. This tends to merge DPUs, which have intensive data-exchange between them. The generated hardware through IAPO approach consumes 53% less power in interconnects while 26% less overall power as compared to interconnect-unaware design generated by SCALP. 3.2.3 LOPASS The number of input ports of the multiplexers present in a circuit can greatly affect the size of the FPGA resources needed to implement that circuit. Resultantly, this could lead to a higher power consumption. Chen et al. [27] proposed LOPASS, a lowpower HLS tool that is suitable for FPGA architectures and targets data-dominated applications also. It uses FDS for early scheduling and simulated annealing engine for resource allocation and binding. It uses function unit optimizations such as merge, split, reselect, swap and mix (at random) to generate new solutions. After each step of optimization, list scheduling is used to check the overall timing and latency constraints. Since a wide-port multiplexer can be quite expensive in terms of resources on FPGA, a weighted bipartite matching algorithm is used to minimize the number of ports in multiplexers used by the design to finalize the LOPASS flow. The authors showed that LOPASS is able to reduce the power consumption of a design by 35% when compared to the results of Synopsys Behavioral Compiler. 3.2.4 HLS-pg HLS for power-gated circuits is a relatively new domain in HLS tools. The overhead of the state-retention storage required to preserve the circuit state in standby mode is an inherent problem in designing power-gated circuits. Retention storage size reduction is known to be the key factor in minimizing the loss of power-saving (achieved by powergating). The bigger is the size of state-retention storage, the lesser will be the overall benefits of the applied power-gating. Choi et al. [23] targeted a new issue in HLS and proposed an approach that addresses the minimization of the retention storage size

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