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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 64 High-level synthesis and application specific processor design present in a design. They targeted scheduling and resource allocation problem where the scheduling problem targets the minimization of the number of state-retention registers and is solved with an MILP formulation. Register allocation problem is solved using a heuristic vertex coloring algorithm. They showed that for 65 nm CMOS technology, HLS-pg generates circuits with 27% less leakage current and with 6% less circuit area and wire-length, compared to the power-gated circuits produced by conventional HLS. The HLS-pg approach though targets the power-gated specialized hardware synthesis, it is inherently different than our approach as we do not target the HLS of powergated circuits. Instead we use our design-flow to generate non-power-gated hardware micro-tasks and the power-gating is added to our design (at transistor-level) after its generation. Moreover, the benchmarks used by the authors for their experiments (such as IIR7, ELLIPTIC and WAVELET) show that their design-flow is targeted toward data-intensive applications. 3.3 HLS tools targeting other design constraints Though, we are targeting the hardware generation for ultra low-power application domains; however for the sake of completeness, HLS tools targeting other design constraints are also briefly discussed in this action. 3.3.1 Multi-mode HLS Kumar et al. [80] and Chavet et al. [21] targeted a different aspect of HLS applications that focuses on the reconfigurable multi-mode architectures. The multi-mode or multiconfiguration architectures are specifically designed for a set of time-wise mutually exclusive applications (multi-standard applications). Kumar et al. used FDLS algorithm for solving the scheduling problem while HAL is used for resource binding. On the other hand, Chavet et al. used list scheduling algorithm to perform scheduling while a maximal bipartite weighted matching algorithm for resource binding. Although, both of these approaches showed an impressive reduction in area-consumption, they are targeted toward the data-intensive DSP-systems. 3.3.2 Word-length aware HLS Kum et al. [77] tackled another problem existing in embedded systems and combined the word-length optimization of DSP-operators with HLS. Their approach uses an MILP formulation for list scheduling algorithm to solve the scheduling problem while a heuristic-based maximum-clique partitioning algorithm to solve the register-binding problem. It also exploits the datapath merging technique (the concept of datapath merging was introduced by Van der Werf et al. [140]) and selects the largest wordlength operator so that the smaller operations can also be mapped to the same operator if possible. Figure 3.4 shows the basic concept of datapath merging where two different datapaths are merged to generate a single datapath circuit. The cost of this merging is

tel-00553143, version 1 - 6 Jan 2011 HLS tools targeting other design constraints 65 + - x + - x + - Figure 3.4: Dataflow graph (DFG) merging. additional multiplexer as shown in the figure whereas the benefit is the reduction in the number of operators present in a reconfigurable system. The solution by Kum et al. [77] is targeted toward a high throughput design rather than a low-power design. Nevertheless, it gave us an insight that the selection of an optimum word-length for operators could be helpful in reducing the area and power consumed by the hardware micro-task datapath. We have included a bitwidth adaptation stage in our design-flow that is discussed in Section 4.2.3. 3.3.3 Datapath-specification-based HLS Unlike the above-mentioned HLS tools that are based on an iterative-improvementbased techniques, there is a class of HLS tools that take a datapath specification as input and generate the RTL-description in a single step. Two of such tools are discussed in the following sections. 3.3.3.1 User Guided HLS (UGH) Augé et al. [10] proposed a design-flow for User Guided HLS (UGH) for the generation of coprocessors under timing and resource constraints. As compared to other HLS flows, UGH uses a single-step HLS where the datapath is pre-specified by the user at the input of the tool. Hence, the tool is suitable for VLSI designers who have a close knowledge of the actual datapath hardware. It uses two-step scheduling scheme that is further explained below: � Coarse-grain scheduling (CGS): This step implements a list-scheduling-based solution to solve the issue of scheduling, resource allocation and binding. � Fine-grain scheduling (FGS): FGS is performed after an early datapath and its control FSM has been generated. It basically performs retiming in the FSM to meet the actual physical delay constraints of the datapath components to achieve a desired frequency. The UGH synthesis flow is presented in Figure 3.5. It is split into three steps. (i) The CGS generates a datapath and an FSM, called CG-FSM, from the C program and the datapath description. (ii) Then the mapping is performed. Firstly, the generation of the physical datapath is assigned to classical back-end tools using a target cell library. Secondly, the temporal characteristics of the physical datapath are extracted. (iii) MUX x

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