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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 66 High-level synthesis and application specific processor design Behavioral SystemC Subset UGH-CGS Draft Datapath Cell Library Synthesis + Characterization VHDL Datapath VHDL CGFSM UGH-Mapping Depends on back-end synthesis tools Clock Timing Annotations UGH-FGS Figure 3.5: Complete UGH design flow [10]. VHDL Dapath Cycle-accurate SystemC Model VHDL FGFSM Finally, the FGS retimes, for the given frequency, the finite control step machine taking accurately into account the annotated timing delays of the datapath and produces the FG-FSM of the circuit. The notion of FGS and retiming of control FSM could be used in our system to address a different problem that is the optimization of hardware micro-task FSM by merging different FSM-states present in the basic block, of a CDFG, to have a possible reduction in number of FSM-states to reduce its power consumption. 3.3.3.2 No Instruction-Set Computer (NISC) Reshadi et al. [42] proposed an approach that compiles a C program directly to a datapath and its controller. Since there is no instruction abstraction in this architecture they named it No Instruction-Set Computer (NISC). A datapath specification is provided at the input of the design-flow along with the application. The design-flow performs both scheduling and resource binding simultaneously through ALAP-like algorithm. The control-words generated to manage the datapath are kept in a control-memory. Similar to other HLS tools, the target applications are data-intensive algorithms. The area reduction is achieved by reducing the instruction fetch and decode stage of the processor while a large-size control memory can cause a significant amount of dynamic as well as static power consumption. Figure 3.6 shows the NISC design-flow. 3.3.4 Commercial tools and their application domain After discussing the HLS tools present in the academics, we now present some of the industrial HLS tools and their potential applications. Recent generation of industrial

tel-00553143, version 1 - 6 Jan 2011 Application Specific Instruction-set Processor (ASIP) design 67 constraints datapath selection/ generation application custom datapath cycle-accurate compilation Figure 3.6: NISC design-flow [42]. controller HLS tools, in most cases, uses either ANSI-C, C++, or languages such as SystemC that are based on C or C++ that add hardware-specific constructs such as timing, hardware hierarchy, interface ports, explicit specification of parallelism, and others. Some HLS tools that support C or C++ or derivatives are Mentor’s Catapult-C (C, C++) [92], Forte’s Cynthesizer (SystemC) [40], NEC’s CyberWorkbench (C with hardware extensions) [98], Synfora’s PICO (C) [126], and Cadence’s C-to-Silicon (SystemC) [16]. As far as the application domain of these HLS tools is concerned, examining the technical publications from Mentor Graphics on Catapult-C Synthesis, we found Nokia using HLS to generate hardware implementations of DSP algorithms for wireless communications. Alcatel Space also applied Catapult-C to DSP blocks for power, frequency, and timing recovery. From Forte’s website, we see acknowledgments that Toshiba used the Cynthesizer for H.264 multimedia design. Summarizing these findings, we can see a lot of interest in using HLS for DSP blocks for wireless and wired communications and for image processing [47]. It can be clearly seen for both the academic as well as the commercial tools enumerated above that most of them (except for UGH) focus on data-dominated application domains where the hardware specialization is seen as a mean to improve system efficiency through parallelization. Thus, they are not suitable for control-oriented domains (such as ultra low-power WSN applications) where the focus is power-reduction, instead of an increased system throughput. In this thesis, we tried to fill the gap by introducing a design-flow that performs the hardware specialization for control-oriented applications. In the following part of this chapter, we provide the existing design methodologies, algorithms and tools (both academic and commercial) for ASIP design. 3.4 Application Specific Instruction-set Processor (ASIP) design An ASIP is a processor designed for a particular application or for a set of applications. It exploits special characteristics of application(s) to meet the desired performance, cost and power requirements. ASIPs fill the architectural spectrum between general-purpose

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