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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 68 High-level synthesis and application specific processor design programmable processors and dedicated hardware or ASICs. They provide a compromise between the two approaches, i.e. high flexibility through software programmability (provided by general purpose MCUs) and high performance (high throughput and low energy consumption provided by ASICs). To program an ASIP, the desired algorithm is written in a high-level language (C/C++). It is then translated by a compiler to generate a machine code that can be interpreted by the ASIP. The ASIP compiler needs the precise information about the underlying architecture of the processor and the algorithm must be written in such a fashion to facilitate the work of compiler. The ASIP synthesis tool must be capable of providing a fine blend among the algorithm, the compiler and the architecture to generate a successful ASIP. Moreover, the ASIP design does not mean only to design the underlying architecture, but the ASIP designer must also come up with the corresponding software toolkit (e.g. the compiler, simulator, debugger etc.) that can help a user to benefit from the ASIP. To manually design these software toolkits is a time-consuming, expensive and error-prone process, hence, in the literature the researchers have always provided complete design methodologies to design their ASIPs. These approaches are based on Architecture Description Languages (ADL) that are used to describe the generic architecture of an ASIP and then the automatic design-flow goes down till hardware generation of ASIP along with its associated software toolkit. Some ADLs present in the literature are LISA [58], nML [36], ISDL [50], EXPRESSION [51] and Armor [93]. Most of these tools provide a path to retargetable ASIP compiler generation and only few of them target actual ASIP hardware synthesis. Although, some ASIPs are still designed completely from scratch to meet extreme efficiency demands using the above-mentioned approach. There has also been a strong trend toward the use of partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of Instruction-Set Extension (ISE) techniques. This approach is helpful in reducing the design efforts and “time-to-market” while sacrificing some performance efficiency. In the next part of this section, we briefly discuss the methodologies present in the literature for both the complete as well as partial ASIP design (using ISE). 3.4.1 Methodology for complete ASIP design The ASIP design-flow normally follows a generic design methodology that has been presented in the survey paper by Jain et al. [68]. The authors have identified five major steps during the ASIP design that are briefly discussed in the following paragraphs. � Application analysis: Input to the ASIP design process is an application or a set of applications, along with their data and design constraints. The application is analyzed to gather the desired characteristics that can guide the hardware synthesis as well as instruction set generation. An application written in a highlevel language (HLL) is analyzed statically and dynamically and the analyzed information is stored in some suitable intermediate format, which is used in the subsequent steps.

tel-00553143, version 1 - 6 Jan 2011 Application Specific Instruction-set Processor (ASIP) design 69 Applications and design constraints Object Code Generation Application Analysis Architectural Exploration Instruction Set Generation No Object Code Performance achieved Yes Archi. HW Generation Processor Description Figure 3.7: Design methodology for complete ASIP generation � Architectural design space exploration: First of all, a set of possible architectures is identified for a specific application(s) using the output of previous step as well as the given design constraints. Performance of possible architectures is estimated and suitable architecture satisfying performance and power constraints and having minimum hardware cost is selected. � Instruction-set generation: In the next step, instruction-set is generated for that particular application and for the architecture selected. This instruction set is used during the object code synthesis and hardware synthesis steps. � Object code synthesis: Compiler generator or retargetable code generator is used to synthesize code for the particular application(s). � Hardware synthesis: In this step the hardware is synthesized using the ASIP architectural template and Instruction-Set Architecture (ISA) starting from a description in VHDL/Verilog using standard tools. Figure 3.7 shows the steps involved during the complete ASIP design. A performance evaluation phase exists between the instruction set generation step and code and hardware synthesis steps. This phase tests if the generated ASIP satisfies the desired design constraints or not. If yes, then we continue with code and hardware generation. Else, the process is iterated from the start.

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