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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 70 High-level synthesis and application specific processor design Applications and design constraints No Object Code Generation Object Code Instruction Set Generation Instruction Selection Performance Achieved? Yes Archi. HW Generation Processor Description Figure 3.8: Design methodology for partial ASIP generation 3.4.2 Methodology for partial ASIP design The complete ASIP design methodology consists in designing a complete processor along with its software toolkit to guarantee the harmony between the processor architecture and its compiler. However, the design-flow is not completely automated and certain critical parts of the processor have to be manually implemented as in case of design methodology using LISA [58]. Similarly, every new processor has to be validated and optimized that can cause Non-Recurring Engineering (NRE) costs. To reduce these costs, ISE technique is used where the instruction set of a predefined RISC-like processor is extended with special instructions that can be run on a coprocessor generated through the partial ASIP design-flow. Figure 3.8 presents the main steps involved in the design-flow of an extended processor core generation. These steps are briefly discussed in the following paragraphs. � Instruction generation: In first step, the application code is analyzed and specialized instructions are generated for that particular application and for the architecture selected. � Instruction selection: In the next step, a sub-set of these special instructions is selected to efficiently implement the required function under the design constraints provided at the beginning. Like the design-flow for complete ASIP design, this process can be iterative until the required constraints are met. � Object code synthesis: Compiler generator or retargetable code generator is

tel-00553143, version 1 - 6 Jan 2011 Application Specific Instruction-set Processor (ASIP) design 71 used to synthesize code for the particular application(s). � Hardware synthesis: In this step the hardware is synthesized using the coprocessor architectural template and ISE starting from a description in VHDL/Verilog using standard tools. The next section briefly presents the existing algorithms involved in different steps of ASIP design, such as instruction selection and register allocation. 3.4.3 Instruction selection Instruction selection is the stage of a compiler back-end that transforms the Intermediate Representation (IR) (like CDFG), of an input application code, into a machinespecific IR that is very close to its final target language. In a typical compiler, it precedes register allocation, so its output IR has an infinite number of pseudoregisters; otherwise, it closely resembles the target assembly language. It works by covering the intermediate representation with patterns. The best covering is the one that results in the fewest patterns being generated for a given IR. A pattern is a template that matches a portion of the IR and can be implemented with a single machine instruction. There are two approaches to perform the covering of an IR: (i) through instruction selection on trees and (ii) through instruction selection on Data Acyclic Graphs (DAGs). Instruction selection on DAGs is a much more computationally difficult problem than instruction selection on expression trees. In has been shown in literature that the former is an NP-Complete problem whereas the latter can be solved in polynomial time [76]. In the following section, we will first discuss the DAG-based instruction selection and existing algorithms to solve this problem. Tree-based instruction selection and its corresponding algorithms are discussed afterward. 3.4.3.1 DAG-based instruction selection DAG-based instruction selection results in a much more efficient covering as the IR of an application code can be covered with a less number of patterns. For example, Figure 3.9 shows the basic butterfly operation performed in FFT (Fast Fourier Transform) algorithm. This operation has multiple outputs and thus it cannot be covered with a single tree-based pattern, whereas it is possible to cover it with a single DAG-based pattern. Hence, a DAG-based instruction selection results in a better covering with lesser number of output patterns. However, it is computationally much more complex to perform DAG-based instruction selection and lies in the domain of NP-Complete problems. Hence, several heuristic algorithms have been developed to provide an approximate solution. In the following paragraphs, we discuss some of the existing algorithms that are being used for instruction selection on DAGs. Simulated annealing: Simulated annealing is a meta-heuristic approach inspired by a process used in metallurgy. This process consists of alternating cycles of slow

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