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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011

tel-00553143, version 1 - 6 Jan 2011 Abstract Wireless Sensor Networks (WSN) are a fast evolving technology having a number of potential applications in various domains of daily-life, such as structural and environmental monitoring, medicine, military surveillance, robotic explorations etc. Engineering a WSN node hardware platform is known to be a tough challenge, as the design must enforce many severe constraints. For example, since WSN nodes must have small form-factors and limited production cost, it is not possible to provide them with large energy sources. In most cases they must rely on non-replenishing (e.g. battery) or self-sufficient (e.g. solar cells) sources of energy. As WSN nodes may have to work unattended for long durations (months if not years), their energy consumption is often the most critical design parameter. Moreover, as a WSN node remains idle during most of its life-time (with a duty cycle of less than 1%), special measures have to be taken to avoid the high static energy dissipation. WSN node devices have until now been designed using off-the-shelf low-power microcontroller units (MCUs) (such as the MSP430, the ARM-Cortex-M0 or the ATMega128L). These MCUs provide a reasonable processing power with low power consumption at an affordable cost. However, they are not necessarily wellsuited for WSN node design as they are based on a general purpose compute engine. In this thesis, we propose a complete system-level design-flow for an alternative approach based on the concept of power-gated hardware micro-tasks. In this approach, computation and control part of a WSN node is made of several hardware micro-tasks that are activated on an event-driven basis, each of them being dedicated to a specific task of the system (such as event-sensing, low-power MAC, routing, and data processing etc.). By combining hardware specialization with power-gating, we can drastically reduce both dynamic and static energy of the WSN node. Following the philosophy of many WSN software frameworks, our design-flow uses a combination of a textual Domain Specific Language (DSL) for system-level specifications (interactions between micro-tasks, event management, shared resources management etc.) and ANSI-C for specifying the behavior of each micro-task. Starting from these specifications and by using Model Driven Engineering (MDE) and retargetable compilation techniques, we are able to generate a synthesizable VHDL description of the whole computation and control subsystem of a WSN node. This VHDL description provides a direct path to ASIC/FPGA implementation. For experimental validation of the approach, first of all, we performed SPICE transistorlevel simulations to study the feasibility of using power-gating in our system. We found that the power-gating scheme happens to have very short switching-time delays, in the orders of a few hundred of nano-seconds. This improves the wake-up response time by at least 50% when compared to low-power MCUs such as the MSP430. A case-study example of a WSN application was conceived and by using our design-flow, VHDL codes for different hardware micro-tasks and system monitor were obtained. The synthesis results show that dynamic power savings by one to two orders of magnitude are possible w.r.t. MCU-based implementations. Similarly, static power savings of one order of magnitude are also obtained due to the reduction in data memory size and power-gating.

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