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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 74 High-level synthesis and application specific processor design Pattern # 1 2 3 4 5 6 7 8 Label Pattern Cost goal reg reg reg Reg Int Fetch reg addr Plus reg reg reg addr reg addr Int Plus addr reg Int (0) (0) (1) (2) (2) (0) (0) Figure 3.10: Sample machine instruction template. Fetch Fetch + #2 #3 Reg Int #6 #4 #4 #5 Figure 3.11: Two possible coverings of the identical tree with different patterns. Reg (0) #2 Fetch Fetch + #8 #4 #4 Int

tel-00553143, version 1 - 6 Jan 2011 Application Specific Instruction-set Processor (ASIP) design 75 Rule # 1 2 3 4 5 6 7 8 Simple Grammar L.H.S R.H.S. goal reg reg Reg reg Int reg Fetch(Addr) reg Plus(reg,reg) addr reg addr Int addr Plus(reg, Int) Cost (0) (0) (1) (2) (2) (0) Figure 3.12: Simp1e grammar and its normal form [114] The input to the BURG-generator is a set of rules. Each rule is a quadruplet of the form R = (P, S, C, A) where P is a pattern existing in the IR, S is the replacement symbol, C and A are the cost and action taken if the given rule is selected. To further elaborate, S is a nonterminal symbol whereas A can be, for instance, the resultant machine instructions generated if the concerning rule is selected for the given pattern. In addition the rules are defined by keeping in mind the underlying hardware of the datapath executing these instructions. Figure 3.12 gives a sample grammar. The nonterminal is on the left side of the rule, the linearized tree pattern is on the right side. In this grammar, goal, reg, and addr are nonterminals. In addition to nonterminals, the grammar has operators. For instance, Reg, Int, Fetch, and Plus are some operators present in the sample grammar. A least-cost parse can be found using dynamic programming. By using all matching patterns at all nodes, it is possible to remember the rules that lead to the least-cost derivation for each possible nonterminal. Figure 3.13 applies the rules in Figure 3.12 to a tree representing Fetch(Fetch(Plus(Reg, Int))). We have only highlighted the possible matches present at Reg and Int nodes. In this example, a BURS matcher finds the least-cost parse of an expression tree to reduce all the nodes to the goal nonterminal. Each node is labeled with a state that contains all the rules that lead to the reduction of this node to all the possible nonterminals. For example, it is possible to reduce the node Int, to all the nonterminals. Int can be reduced to the nonterminals reg and addr, by directly applying the rules 3 and 7 respectively. The costs associated with each derivation is the cost of that particular rule. The reduction toward goal utilizes the rule, “goal → reg” that will require that Int to be subsequently reduced to reg. Therefore, while the cost associated with rule 1 is 0, the total cost of the reduction from Int to goal is 1. 3.4.4 Register allocation The resource allocation problem relates to simple register allocation in ASIPs that have single processing element, while in ASIPs that have Very Large Instruction Word (0) (0)

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