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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 76 High-level synthesis and application specific processor design (All rules for covering Fetch) (goal reg #1, 0; reg Reg #2, 0; addr reg #6, 0) Fetch (All rules for covering Fetch) Fetch Plus Reg Int (All rules for covering Plus) (goal reg #1, 0; reg Int #3, 1; addr Int #7, 0) Figure 3.13: Dynamic programming applied to example tree, each node labeled with “(Rule, Cost)”. (VLIW) architecture, it also consists in functional unit allocation. As we described in previous section that instruction selection results in an assembly-level IR that contains infinite number of pseudoregisters. The allocation of the limited number of physical registers present in the register file of an ASIP to these infinite pseudo-registers is called register allocation. Similar algorithms are used in ASIP design-flow for register allocation as those were used in HLS design-flow (see Section 3.1.4). After a thorough description of ASIP design-flows and their related algorithms, we move on to present some existing work in the domain of ASIP design tools. 3.5 Existing tools in ASIP design There exist in the literature several commercial as well as academic examples of configurable ASIPs. Xtensa by Gonzalez is a configurable and extensible coprocessor core that builds around a traditional RISC five-stage pipeline [46, 128]. Silicon Hive is a commercial tool that generates a framework of multiple ULIW (Ultra Large Instruction Word) coprocessors [124]. Virage Logic [141] has also launched a series of commercial ASIPs like ARC750, ARC700 etc. In addition, different FPGA vendors have launched their specialized soft-cores that can be implemented on their FPGAs. Most famous of these FPGA-based soft-cores are NIOSII by Altera [6] and MicroBlaze by Xilinx [144]. Aeroflex Gaisler [2] has introduced LEON series of soft-cores that are based on SPARC V8 processor architecture. The FPGA-based soft-cores provide flexibility and can be used for rapid prototyping. However, evidently they are consume more power and provide less performance as compared to ASIC-based ASIPs. 3.5.1 ICORE As far as low-power ASIP development is concerned, Glöker et al. proposed ICORE [45], a low-power ASIP specialized for the data-intensive application of a DVB-T receiver. Their design methodology starts with a semi-custom design and instruction-set en

tel-00553143, version 1 - 6 Jan 2011 General discussion 77 hancements (hardware acceleration) are applied to this unoptimized architecture to achieve a desired speed-up. When all the timing constraints are fulfilled, additional optimizations are applied to increase the power-efficiency. The authors used two simple rules to apply these optimizations: (i) they tried to find a power optimized (hardware accelerated) solution for the most frequently used patterns, (ii) if there existed a simple hardware solution for even a less-frequent task, it was still implemented in hardware to save power. They synthesized an ICORE architecture using 0.18 µm 5-metal layer technology. ICORE was able to get a speed-up of nearly 15x when compared to traditional DSP with only a slight increase in average power whereas the overall energy is reduced by 92.5% as the total time taken to do the job is considerably reduced. On the other hand, Kin et al. [74] also proposed a framework for rapidly exploring the design space of power-efficient mediaprocessors in the domain of VLIW and SIMD (Single Instruction Multiple Data) architectures. Their framework is based on the idea of using a retargetable Instruction Level Parallelism (ILP) compiler and its corresponding processor simulator to perform rapid prototyping of media application benchmarks. They used StrongARM SA-110 as their baseline architecture and their framework exploited the ILP compiler to perform the design space exploration of multi-processor platforms to generate power-efficient mediaprocessors. 3.5.2 Soft-core generator Fin et al. [37] introduced the concept of soft-core generation by instruction-set analysis. The soft-core generator can be easily applied for parameterization and designing any kind of processor which can be described by using FSMDs (FSMs with datapaths). By using different parameters at the input of the soft-core generator design-flow, several soft-cores performing the selected instruction sub-sets are generated. The VHDL codes for these soft-cores are then easily synthesized to find the area-reduction caused by the specialization process. 3.6 General discussion Interestingly, all these ASIP design and HLS tools share a common characteristic: they generate the hardware that is specialized toward data-intensive applications and they generally see hardware specialization as a mean to improve performance over a standard software implementation. This performance improvement, however, often comes at a price of increased area cost (coprocessor or ISE requires additional area). Of course, these specializations also have a significant impact on power efficiency, since they allow for a drastic reduction of dynamic power of the system, however, the overall static power dissipation of the system is increased due to the increase in overall silicon area. This increased static power can be crucial for a power-restricted application domain such as WSN. Indeed, except from [37] and [86], very few papers have addressed the problem of using processor specialization as a mean to reduce silicon footprint. We believe that in the context of WSN node architecture, where silicon area and ultra low-power are the

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