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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 78 High-level synthesis and application specific processor design two main design issues, such an approach deserves attention. In the next chapter, we present an original approach which builds on this idea. We propose a new architectural model (along with a complete system-level downto RTL design-flow) for WSN node controller design, based on the notion of concurrent power-gated hardware micro-tasks.

tel-00553143, version 1 - 6 Jan 2011 Chapter 4 Hardware micro-task synthesis This chapter discusses in details our proposed design-flow for hardware micro-task synthesis as highlighted in Figure 4.1. The chapter starts with the notion of hardware micro-task where we provide the potential power benefits and architectural details of the proposed hardware micro-task. Our proposed design-flow for C to RT-level VHDL description of hardware micro-task synthesis is discussed afterward. Incidentally, we would like to clear it out that we do not propose new algorithms to solve different HLS/ASIP-design related problems such as instruction selection or register allocation, instead we use classical algorithms to solve these problems. The choice of using classical tools is mainly driven by our application domain that consists in control-oriented tasks of a WSN node. Since the target applications are not data-intensive, working on more sophisticated algorithm development would not be more beneficial. The chapter concludes with an example of a control-oriented micro-task (processed through our tool) showing the benefits of our approach over a conventional MCU-based software implementation. 4.1 Notion of hardware micro-task In a typical WSN node, each task present in the Task Flow Graph (TFG) is handled by an MCU and corresponding OS that provides support for multi-tasking features. We call such task, a micro-task, to highlight the fact that it has light-weight processing requirements. In addition, these micro-tasks normally have a run-to-completion semantic. Figure 4.3 shows the generic template of a micro-task. In our approach, each micro-task present in the TFG is executed by a specialized hardware entity. This entity is called a “hardware micro-task”. 4.1.1 Potential power benefits Some of the important aspects of the hardware micro-task design that impact its overall power and energy consumption are discussed in the following section. 79

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