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Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

Synthèse de haut-niveau de contrôleurs ultra-faible consommation ...

tel-00553143, version 1

tel-00553143, version 1 - 6 Jan 2011 82 Hardware micro-task synthesis Micro- Task Ram Address (Caculated) Ram Input Selection ramDataIn Rom Address Alu Result I/O Peripherals CTRL. FSM 3 2 Task in C with a run-to-completion Ram Address (Generated) en_MT 8 Vdd Vvdd void encipher(unsigned 8 long * v,unsigned long * w) { unsigned long Register y=v[0],z=v[1],sum=0,delta=0x9E3779B9, File rfDataOut a=k[0],b=k[1],c=k[2],d=k[3],n=32; RAM while(n-->0){ 8 ramDataOut sum += delta; 8 2y += (z > 5)+b; 8 z += (y ROM > Arithmetic 5)+d; } Logic Unit (ALU) w[0]=y; w[1]=z; } Operand A Adr. semantic Operand B Adr. Alu Input Selection Alu Operand Select Pheripheral On/Off Figure 4.3: Generic template of a “micro-task” running in a WSN node. 4.1.1.1 Simplified architecture In contrast to an instruction-set processor, the program of a hardware micro-task is hard-wired into an FSM that directly controls a semi-custom datapath. This makes the architecture much more compact (no need of an instruction decoder or instruction memory) and allows the size of storage devices (register file and ROM) as well as the ALU functions to be customized to the target application. Each of these hardware micro-tasks can access shared data memory and I/O peripheral (e.g. SPI link to an RF transceiver). The simplicity of the hardware micro-task architecture w.r.t. a generic architecture of an MCU (currently being used in WSN node design) can be seen in Figure 4.2. These general purpose MCUs are not customized to the application at hand and of course contain an instruction memory, fetch and decode stage. Whereas, our datapath contains neither instruction memory nor fetch/decode stage, and it can be customized to the application at hand. This leads to a reduction in both dynamic and static power consumption. Such a drastically simplified architecture allows for obvious dynamic power savings compared to a standard MCU architecture, with a negligible loss in performance since the datapath is tailored to the application at hand. 4.1.1.2 Exploiting the run-to-completion semantic As mentioned earlier, the micro-tasks follow a run-to-completion semantic. This leads to a stateless execution of the micro-tasks in which we do not need to store the state of the local variables present in the C-specification of a micro-task after its execution. In hardware implementation, it means that the whole micro-architecture of the hardware micro-task can be power-gated after its job-termination that leads to a lower static power dissipation.

tel-00553143, version 1 - 6 Jan 2011 Notion of hardware micro-task 83 Hardware micro-task Ram Address (Caculated) Ram Input Selection 2 ramDataIn Shared RAM IFace Ram Address (Generated) Register File romDataOut 8 Imm. ROM Arithmetic Logic Unit (ALU) Rom Address en_MT 8 ramDataOut 8 Vdd Operand A Adr. Vvdd CTRL. FSM Operand B Adr. rfDataOut 8 Alu Input Selection Alu Result 3 8 2 Alu Operand Select Pheripheral On/Off Figure 4.4: Architecture of a generic hardware micro-task. 4.1.1.3 Micro-task granularity Hardware specialization can be less effective if more and more functionalities are handled by the same specialized hardware. As a consequence, to take advantage from hardware specialization, we need to distribute the whole WSN node software framework into a set of hardware micro-tasks, so as to maintain a high degree of specialization within each micro-task. For instance, a complete WSN communication stack uses approximately 3500 instructions; by distributing the stack functionality onto 7 micro-tasks, we can reach an average micro-task code size of 500 instructions, which is a granularity level at which we can expect significant energy improvements. Since the micro-tasks present in WSN applications are fine-grain in nature with an average code size much smaller than 500 instructions (as shown in Chapter 6), we benefit from a higher degree of hardware specialization. 4.1.1.4 Simplified access to shared resources It is also worth-mentioning that the local variables present in the C-specification of a micro-task are stored in the register file while the global variables are stored in external memory blocks that can be shared between multiple hardware micro-tasks. Depending upon the life-time of these global variables, these external memories can be power-gated Shared I/O IFace

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