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Speculative Instruction Validation for Performance-Reliability Trade-off

Speculative Instruction Validation for Performance-Reliability Trade-off

BranchMispred./CorrectResult/DetectedbyValidator Arch. Source Phys. Source Operand Value Result Value Arch. Dest Total vpr 30 / 5 / 64 22 / 7 / 70 15 / 6 / 79 8 / 0 / 92 24 / 4 / 71 21 / 4 / 72 gcc 9 / 1 / 90 5 / 2 / 93 5 / 1 / 94 1 / 0 / 99 13 / 3 / 84 7 / 1 / 92 mcf 34 / 5 / 60 28 / 4 / 67 15 / 4 / 80 6 / 0 / 94 38 / 2 / 58 26 / 3 / 69 parser 40 / 4 / 55 28 / 4 / 65 22 / 7 / 70 13 / 0 / 87 35 / 3 / 60 30 / 4 / 63 vortex 14 / 3 / 82 7 / 4 / 88 8 / 2 / 90 2 / 0 / 98 13 / 8 / 79 10 / 3 / 86 bzip2 17 / 6 / 76 11 / 7 / 80 11 / 13 / 75 4 / 0 / 96 15 / 3 / 81 13 / 6 / 80 wupwise 0 / 2 / 98 0 / 0 / 100 0 / 6 / 94 0 / 0 / 100 0 / 2 / 98 0 / 2 / 98 swim 3 / 9 / 87 2 / 9 / 88 1 / 13 / 86 1 / 0 / 99 3 / 17 / 79 2 / 9 / 88 mgrid 0 / 3 / 96 0 / 2 / 98 0 / 2 / 98 0 / 0 / 100 0 / 2 / 97 0 / 2 / 98 applu 1 / 2 / 97 0 / 2 / 97 0 / 9 / 91 0 / 0 / 100 0 / 3 / 97 0 / 3 / 96 mesa 43 / 7 / 49 33 / 6 / 60 30 / 14 / 56 27 / 0 / 73 38 / 7 / 54 36 / 7 / 51 art 7 / 9 / 83 3 / 11 / 86 4 / 10 / 86 2 / 0 / 98 10 / 4 / 85 5 / 7 / 87 equake 21 / 9 / 68 12 / 10 / 74 7 / 7 / 85 3 / 0 / 96 17 / 5 / 76 13 / 6 / 77 ammp 4 / 5 / 90 5 / 10 / 84 2 / 5 / 93 1 / 0 / 99 5 / 7 / 88 3 / 5 / 92 apsi 14 / 9 / 77 6 / 9 / 84 6 / 9 / 85 3 / 0 / 97 10 / 6 / 83 9 / 7 / 83 Average 16 / 5 / 78 11 / 6 / 82 8 / 7 / 84 5 / 0 / 95 15 / 5 / 79 12 / 5 / 82 Table5.Percentagesoferrors(outofthosethatpropagatetomainthreadinstructions)thatareeither maskedordetected and (iii) five-bit counters that are incremented by one and decremented by three and a confidence threshold of 15. Table 6 shows the results for the 2-bit counter; the results for others were very similar. Redundantly executing control instructions with a low confidence in successful validation only slightly reduces the average total undetected error rate in Table 4 to 0.42%, while the average reduction in the performance impact of SRT reduces to about 52% when conserving the fetch to decode bandwidth. Henceforth, we do not use confidence in control instructions for better reliability. 5.2 Reliability Trade-off For Better Performance – Low Reliability Impact AvoidingRedundancyforProducersofSuccessfully ValidatedInstructions: The SpecIV technique has an extremely low undetected error rate because it is highly unlikely that a faulty instruction generates an expected result. Similarly, it is highly unlikely that if an instruction is successfully validated, then the instructions producing its operands are executed incorrectly. For instance, we observe in SpecIV that errors in architectural destination register identifiers almost always lead to failed validations of their dependants. Hence, we extend SpecIV such that if an instruction is successfully validated, then even the instructions producing its operands are not redundantly executed. To implement this technique, we provide aRe-executeBit-vectorIndexTable (RBIT) in the commit stage.RBIT consists of one entry for each architectural register. Each entry stores the re-execute bit-vector index of the instruction producing that architectural register. Each main thread instruction updates the RBIT entry of its destination at commit. This optimization does not require any additional hardware. If a main thread instruction is successfully validated, then in parallel to resetting its reexecute bit, it also resets the re-execute bits at the indices present in the RBIT entries of its source architectural registers. In this technique, all main thread instructions write their results in the CVQ (and their destination register identi- fiers in DIQ when conserving the fetch to decode bandwidth) because even if instructions are not successfully validated, their redundant counterparts may not be executed because their dependants are successfully validated. This technique increases the processor vulnerability by removing more instructions from the sphere of replication. Committing Main Thread Instruction Current Instruction Re−execute bit−vector Producers RBIT Figure6.AvoidingRedundancyforProducers ofSuccessfullyValidatedInstructions Our experiments show that this technique avoids redundant execution of an average of about 69% instructions. This results in about 58% performance impact reduction, about 62% when conserving fetch to decode bandwidth, while increasing the undetected error rate from about 0.45% to about 0.5%. However, if the reliability improving techniques of Section 5.1 are combined with this technique, we observed an average undetected instruction error rate of only about 0.09% with an average of about 60% performance impact reduction in SRT. SpecIVWithMulti-ValueValidator(SpecIV-MV): One method to increase the validation success rate, so as to further reduce the performance impact, is to maintain a larger set of expected values. An instruction’s validation succeeds if its result matches any of the expected values. The chances of an 412 0 1 31

Non-controlInstructions ControlInstructions OutofTotal No Zero Non-zero OutofTotal Low High (WithinCategory) stride stride stride (WithinCategory) Conf. Conf. vpr 46 ( 0.6 ) 82 18 0 54 ( 3.5 ) 31 69 gcc 13 ( 0.0 ) 89 11 0 87 ( 2.7 ) 27 73 mcf 48 ( 1.0 ) 94 5 1 4 ( 2.3 ) 17 83 parser 27 ( 0.3 ) 95 4 1 73 ( 3.9 ) 18 82 vortex 13 ( 0.1 ) 98 2 0 87 ( 2.5 ) 42 58 bzip2 53 ( 0.7 ) 88 9 3 47 ( 3.1 ) 28 72 wupwise 100 ( 0.0 ) 100 0 0 0 ( 0.0 ) 0 10 swim 94 ( 0.5 ) 77 20 3 6 ( 0.2 ) 18 82 mgrid 88 ( 0.0 ) 44 34 22 12 ( 0.3 ) 5 95 applu 57 ( 0.2 ) 78 22 0 43 ( 11.9 ) 0 100 mesa 65 ( 0.3 ) 95 4 1 35 ( 0.6 ) 39 61 art 63 ( 0.3 ) 39 58 3 37 ( 1.9 ) 16 84 equake 77 ( 2.2 ) 79 11 10 23 ( 5.7 ) 4 96 ammp 41 ( 0.1 ) 87 12 1 59 ( 0.7 ) 7 93 apsi 44 ( 0.3 ) 89 9 2 56 ( 3.5 ) 38 62 Average 55 ( 0.5 ) 82 15 3 45 ( 2.9 ) 19 81 Table6.Confidenceinsuccessfulvalidationsforundetectederrorsfrommainthreadinstructions instruction’s incorrect result matching an expected value also increases, thus reducing reliability. In SpecIV-MV, we maintain an additional direct mapped 1K-entry validator which records the last four distinct values in each entry for those instructions whose validations fail in the main validator. We observed that SpecIV-MV was not very effective as compared to SpecIV because it further reduces the performance impact of SRT by only about 2%, while increasing the average undetected errors from about 0.45% to about 0.91%. We also experimented with storing last four strides instead of values, but it performed worse that SpecIV-MV. 5.3 Reliability Trade-off For Better Performance – High Reliability Impact PartialResultValidation: Another method to relax the conditions for successful validations is to validate only a subset of result bits. This approach increases vulnerability because of the inability to detect errors in the ignored bits and can have a high reliability impact depending on the number of bits ignored. Figure 7 plots the average percentage performance impact reduction and the average undetected instruction error rate when validating only the least significant 16, 20, 24, and 28 result bits and also when validating all the bits for the base SpecIV. A 64-bit result is treated as two 32-bit results. The average performance impact reduction increases from about 54% to about 69% when the validated bits are reduced from 32 to 16, and the average total undetected instruction error rate increases from about 0.45% to about 10%. When validating fewer bits, the machine becomes more susceptible to errors in operand and result values because errors in them directly correspond to errors in the results. For instance, errors in the higher order bits of operands lead to errors in the higher order bits of results, which may be ignored in this scheme resulting in undetected errors. The errors in register identifiers, on the other hand, impact random bits in the results. Average Perf. Impact Reduction Average Error Rates 75 60 45 30 15 0 20 15 10 5 Average Performance Impact Reduction Src Arch Reg Mapping Error Src Phys Reg Mapping Error Operand Value Error Result Value Error Dest Arch Reg Mapping Error Total Errors 16 20 24 28 All 16 20 24 Total Bits Validated 28 All Figure 7. Undetected Instruction Error Rate andPerformanceImpactReductionofPartial ResultValidation ResultValueWidthandStrideWidthValidation: In these techniques, an instruction is not re-executed if its result’s width matches the expected width (SpecIV-RW) or the width of its result’s difference from the last result matches the expected width (SpecIV-SW). These validations are performed for only those instructions whose result value validations fail. Each validator entry is augmented to store either the last result’s width for that entry in SpecIV-RW or the width of the difference in the two most recent result values (Stride Width) for that entry in SpecIV-SW. Width of a value is determined by the position of the most significant ’1’ in its representation. We also define width granularity that specifies the acceptable variations in width. For instance, if the width of an expected value is 4, then values with widths 3, 4, and 5 result in successful validations for a width granularity of 2, and values with width 2,3,4,5, and 6 result in successful validations for a width granularity of 4. Figure 8 shows the average total undetected instruction error rates and average percentage reduction in performance impact of SpecIV-RW and SpecIV-SW for width granularities of 2, 4 and 8, on top of the base SpecIV. For SpecIV-RW, 413

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