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section 1 - World Intellectual Property Organization

section 1 - World Intellectual Property Organization

44/2002 21950 PCT

44/2002 21950 PCT Gazette - Section I - Gazette du PCT 31 Oct/oct 2002 AT LIMITED, 2381-1, Kitagejo, Fujii-cho, Nirasaki-shi, Yamanashi 407-8511 (JP). (74) SUYAMA, Saichi; Kanda Higashiyama Bldg., 1, Kandata-cho 2-chome, Chiyoda-ku, Tokyo 101-0046 (JP). (81) CN KR US. (84) EP (AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR). (51) 7 H01L 21/316 (11) WO 02/086958 (13) A1 (21) PCT/EP02/04345 (22) 19 Apr/avr 2002 (19.04.2002) (25) de (26) de (30) 101 19 741.1 23 Apr/avr 2001 DE (23.04.2001) (43) 31 Oct/oct 2002 (31.10.2002) (54) METHOD AND DEVICE FOR THE PRODUCTION OF PROCESS GASES PROCEDE ET DISPOSITIF PERMET- TANT DE PRODUIRE UN GAZ DE TRAVAIL (71) MATTSON THERMAL PRODUCTS GMBH [DE/DE]; Daimlerstrasse 10, 89160 Dornstadt (DE). (for all designated States except / pour tous les États désignés sauf US) (72, 75) ROTERS, Georg [DE/DE]; Weseler Strasse 37, 48249 Dülmen (DE). MADER, Roland [DE/DE]; Ursulers 2, 87452 Altusried (DE). SOMMER, Helmut [DE/DE]; Haldenweg 9, 73326 Deggingen (DE). ER- LIKH, Genrih [US/US]; 377 Michelle Lane, Daly City, CA 94015 (US). PASHUT, Yeh uda [US/US]; 570 Crystalberry Terrace, San Jose, CA 95129 (US). (81) CA CN IL JP KR SG US. (84)EA(AMAZBYKGKZMDRUTJTM);EP (ATBECHCYDEDKESFIFRGBGRIE IT LU MC NL PT SE TR). Published / Publiée : (c) (51) 7 H01L 21/321 (11) WO 02/086959 (21) PCT/US02/09180 (13) A2 (22) 27 Mar/mar 2002 (27.03.2002) (25) en (26) en (30) 09/818,751 27 Mar/mar 2001 (27.03.2001) US (43) 31 Oct/oct 2002 (31.10.2002) (54) POST-PLANARIZATION CLEAN-UP NETTOYAGE DE POST-PLANARISA- TION (71) MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way, Boise, ID 83716 (US). (72) ANDREAS, Michael, T.; 1400 Hill Road, Boise, ID 83702 (US). (74) LEFFERT, Thomas, W.; FoggSliferPolglaze Leffert & Jay, P.A., P.O. Box 581009, Minneapolis, MN 55458-1009 (US). (81) AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW. (84)AP(GHGMKELSMWMZSDSLSZTZ UG ZM ZW); EA (AM AZ BY KG KZ MD RU TJ TM); EP (AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR); OA(BFBJCFCGCICMGAGNGQGW ML MR NE SN TD TG). (51) 7 H01L 21/322 (11) WO 02/086960 (21) PCT/US02/12712 (13) A1 (22) 22 Apr/avr 2002 (22.04.2002) (25) en (26) en (30) 60/285,180 20 Apr/avr 2001 (20.04.2001) US (30) 60/345,165 21 Dec/déc 2001 (21.12.2001) US (43) 31 Oct/oct 2002 (31.10.2002) (54) METHOD FOR THE PREPARATION OF A SILICON WAFER HAVING STABI- LIZED OXYGEN PRECIPITATES PROCEDE DE PREPARATION D’UNE PLAQUETTE EN SILICIUM PRESEN- TANT DES PRECIPITES D’OXYGENE STABILISES (71) MEMC ELECTRONIC MATERIALS, INC. [US/US]; P.O. Box 8, 501 Pearl Drive, St. Peters, MO 63376 (US). (72) BORGINI, Marco; c/o MEMC Electronic Materials, S.p.A., Viale Gherzi 31, I-28100 Novara (IT). GAMBARO, Daniela; c/o MEMC Electronic Materials, S.p.A., Viale Gherzi 31, I-28100 Novara (IT). RAVANI, Marco; c/o MEMC Electronic Materials, S.p.A., Viale Gherzi 31, I-28100 Novara (IT). RIES, Michael, J.; 4207 Eagle Rock Court, St. Charles, MO 63304 (US). SACCHETTI, Laura; MEMC Electronic Materials, S.p.A., Viale Gherzi 31, I-28100 Novara (IT). STAN- DLEY, Robert, W.; c/o MEMC Electronic Materials, Inc., 501 Pearl Drive, P.O. Box 8, St. Peters, MO 63376 (US). FALSTER, Robert, J.; 22 Compton Terrace, London N1 2UN (GB). STINSON, Mark, G.; 572 Crestview, East Alton, IL 62024 (US). (74) SCHUTH, Richard, A. et al. / etc.; One Metropolitan Square, Suite 1600, St. Louis, MO 63102 (US). (81) JP KR. (84)EP(ATBECHCYDEDKESFIFRGBGR IE IT LU MC NL PT SE TR). (51) 7 H01L 21/4763, 23/48, C25D 5/02 (11) WO 02/086961 (21) PCT/US02/10500 (13) A1 (22) 4 Apr/avr 2002 (04.04.2002) (25) en (26) en (30) 60/286,273 24 Apr/avr 2001 (24.04.2001) US (30) 10/108,614 27 Mar/mar 2002 (27.03.2002) US (43) 31 Oct/oct 2002 (31.10.2002) (54) ELECTROPOLISHING METAL LAY- ERSONWAFERSHAVINGTRENCHES OR VIAS WITH DUMMY STRUC- TURES POLISSAGE ELECTROLYTIQUE DE COUCHES METALLIQUES SUR DES PLAQUETTES POURVUES DE TRAN- CHEES OU TROUS D’INTERCON- NEXION A FAUSSES STRUCTURES (71) ACM RESEARCH, INC. [US/US]; Suite 610, 46520 Fremont Boulevard, Fremont, CA 94538 (US). (72) WANG, Hui; 38855 Litchfield Court, Fremont, CA 94536 (US). YIH, Peihaur; 37171 Sycamore Street #824, Newark, CA 94560 (US). (74) YIM, Peter, J. et al. / etc.; Morrison & Foerster LLP, 425 Market Street, San Francisco, CA 94105-2482 (US). (81) CA CN IL JP KR SG. (84)EP(ATBECHCYDEDKESFIFRGBGR IE IT LU MC NL PT SE TR). Published / Publiée : (c) (51) 7 H01L 21/66 (11) WO 02/086962 (13) A1 (21) PCT/US02/05949 (22) 25 Feb/fév 2002 (25.02.2002) (25) en (26) en (30) 09/841,762 24 Apr/avr 2001 US (24.04.2001) (43) 31 Oct/oct 2002 (31.10.2002) (54) METHOD AND APPARATUS FOR IM- PROVING RESOLUTION OF OBJECTS IN A SEMICONDUCTOR WAFER PROCEDE ET APPAREIL PERMET- TANT D’AMELIORER LA RESOLU- TION D’OBJETS SUR UNE TRANCHE SEMI-CONDUCTRICE (71) MENTOR GRAPHICS CORPORA- TION [US/US]; 8005 S.W. Boeckman Road, Wilsonville, OR 97070-7777 (US). (for all designated States except / pour tous les États désignés sauf US) (72, 75) PELL, Edwin, A., III [US/US]; 216 Long Pond Road, Rhinebeck, NY 12572 (US). (74) SCOTTI, Robert, F.; Klarquist Sparkman, LLP, One World Trade Center, Suite 1600, 121 SW Salmon Street, Portland, OR 97204 (US). (81) AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW. (84)AP(GHGMKELSMWMZSDSLSZTZ UG ZM ZW); EA (AM AZ BY KG KZ MD RUTJTM);EP(ATBECHCYDEDKES FI FR GB GR IE IT LU MC NL PT SE TR); OA(BFBJCFCGCICMGAGNGQGW ML MR NE SN TD TG). (51) 7 H01L 21/68, 21/02, B65G 49/07 (11) WO 02/086963 (13) A1 (21) PCT/JP02/03391 (22) 4 Apr/avr 2002 (04.04.2002) (25) ja (26) ja (30) 2001-121735 19 Apr/avr 2001 (19.04.2001) (43) 31 Oct/oct 2002 (31.10.2002) JP

44/2002 31 Oct/oct 2002 PCT Gazette - Section I - Gazette du PCT 21951 (54) METHOD OF PRODUCING SEMICON- DUCTOR INTEGRATED CIRCUIT DE- VICE PROCEDE DE PRODUCTION DE DIS- POSITIF A CIRCUIT INTEGRES A SEMI-CONDUCTEURS (71) HITACHI, LTD. [JP/JP]; 6, Kanda Surugadai 4-chome, Chiyoda-ku, Tokyo 101-8010 (JP). (for all designated States except / pour tous les États désignés sauf US) (72, 75) WAKABAYASHI, Takayuki [JP/JP]; C/O Semiconductor & Integrated Circuits, Hitachi, Ltd., 20-1, Josuihoncho 5-chome, Kodaira-shi, Tokyo 187-8588 (JP). UCHINO, Toshiyuki [JP/JP]; C/O Semiconductor & Integrated Circuits, Hitachi, Ltd., 20-1, Josuihoncho 5-chome, Kodaira-shi, Tokyo 187-8588 (JP). KIGUCHI, Yasuo [JP/JP]; C/O Semiconductor & Integrated Circuits, Hitachi, Ltd., 20-1, Josuihoncho 5-chome, Kodaira-shi, Tokyo 187-8588 (JP). KOIKE, Atsuyoshi [JP/JP]; C/O Semiconductor & Integrated Circuits, Hitachi, Ltd., 20-1, Josuihoncho 5-chome, Kodaira-shi, Tokyo 187-8588 (JP). (74) TSUTSUI, Yamato; Tsutsui & Associates, 3F, Azeria Bldg., 1-1, Nishi-shinjuku 8-chome, Shinjuku-ku, Tokyo 160-0023 (JP). (81) CN KR SG US. (84) EP (AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR). (51) 7 H01L 21/768, G09F 9/33, H01L 33/00 (11) WO 02/086964 (13) A1 (21) PCT/JP02/03674 (22) 12 Apr/avr 2002 (12.04.2002) (25) ja (26) ja (30) 2001-120119 18 Apr/avr 2001 JP (18.04.2001) (43) 31 Oct/oct 2002 (31.10.2002) (54) WIRING METHOD AND ELEMENT ARRANGING METHOD USING THE SAME, AND METHOD OF PRODUC- ING IMAGE DISPLAY DEVICES PROCEDE DE CABLAGE ET PROCEDE D’AGENCEMENT D’ELEMENTS FAI- SANT APPEL A CE DERNIER ET PRO- CEDE DE PRODUCTION DE DISPOSI- TIFS D’AFFICHAGE D’IMAGES (71) SONY CORPORATION [JP/JP]; 7-35, Kitashinagawa 6-chome, Shinagawa-ku, Tokyo 141-0001 (JP). (for all designated States except / pour tous les États désignés sauf US) (72, 75) YANAGISAWA, Yoshiyuki [JP/JP]; c/o SONY CORPORATION, 7-35, Kitashinagawa 6-chome, Shinagawa-ku, Tokyo 141-0001 (JP). IWAFUCHI, Toshiaki [JP/JP]; c/o SONY CORPORATION, 7-35, Kitashinagawa 6-chome, Shinagawa-ku, Tokyo 141-0001 (JP). (74) NAKAMURA, Tomoyuki; c/o Miyoshi International Patent Office, 9th Floor, Toranomon Daiichi Building, 2-3, Toranomon 1-chome, Minato-ku, Tokyo 105-0001 (JP). (81) AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW. (84)AP(GHGMKELSMWMZSDSLSZTZ UG ZM ZW); EA (AM AZ BY KG KZ MD RU TJ TM); EP (AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR); OA(BFBJCFCGCICMGAGNGQGW ML MR NE SN TD TG). (51) 7 H01L 21/8246, 27/115, 21/768 (11) WO 02/086965 (13) A1 (21) PCT/IT01/00192 (22) 19 Apr/avr 2001 (19.04.2001) (25) it (26) en (43) 31 Oct/oct 2002 (31.10.2002) (54) CONTACT STRUCTURE FOR AN INTEGRATED SEMICONDUCTOR DE- VICE STRUCTURE DE CONTACT POUR DISPOSITIF INTÉGRÉ À SEMI-CONDUCTEUR (71) STMICROELECTRONICS S.R.L. [IT/IT]; Via C. Olivetti, 2, I-20041 Agrate Brianza (IT). (for all designated States except / pour tous les États désignés sauf US) (72, 75) ZAMBRANO, Raffaele [IT/IT]; Via Petrone, 69, I-95029 Viagrande (IT). AR- TONI, Cesare [IT/IT]; Via N. Di Franco, 46, I-96011 Augusta (IT). CORVASCE, Chiara [IT/IT]; Via Pacini, 10, I-95124 Catania (IT). (74) JORIO, Paolo et al. / etc.; Studio Torta S.r.l., Via Viotti, 9, I-10121 Torino (IT). (81) AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW. (84)AP(GHGMKELSMWMZSDSLSZTZ UG ZW); EA (AM AZ BY KG KZ MD RU TJ TM); EP (AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR); OA (BFBJCFCGCICMGAGNGWMLMR NE SN TD TG). (51) 7 H01L 21/8247, 27/115 (11) WO 02/086966 (21) PCT/IB02/01353 (13) A1 (22) 16 Apr/avr 2002 (16.04.2002) (25) en (26) en (30) 01201434.6 20 Apr/avr 2001 (20.04.2001) EP (43) 31 Oct/oct 2002 (31.10.2002) (54) TWO-TRANSISTOR FLASH CELL HAVING VERTICAL ACCESS TRAN- SISTOR CELLULE DE MEMOIRE FLASH A DEUX TRANSISTORS COMPORTANT UN TRANSISTOR D’ACCES VERTI- CAL (71) KONINKLIJKE PHILIPS ELECTRON- ICS N.V. [NL/NL]; Groenewoudseweg 1, NL-5621 BA Eindhoven (NL). (72) VERHAAR, Robertus, D., J.; Prof. Holstlaan 6, NL-5656 AA Eindhoven (NL). (74) DUIJVESTIJN, Adrianus, J.; Internationaal Octrooibureau B.V., Prof. Holstlaan 6, NL-5656 AA Eindhoven (NL). (81) JP KR. (84)EP(ATBECHCYDEDKESFIFRGBGR IE IT LU MC NL PT SE TR). (51) 7 H01L 23/00 (11) WO 02/086967 (13) A2 (21) PCT/EP02/04308 (22) 18 Apr/avr 2002 (18.04.2002) (25) de (26) de (30) 101 19 873.6 24 Apr/avr 2001 (24.04.2001) DE (43) 31 Oct/oct 2002 (31.10.2002) (54) METHOD FOR PRODUCING METAL- LIC BIT LINE CONTACTS PROCEDE DE PRODUCTION DE CONTACTS DE LIGNES DE BITS METALLIQUES (71) INFINEON TECHNOLOGIES AG [DE/DE]; St.-Martin-Str. 53, 81669 München (DE). (for all designated States except / pour tous les États désignés sauf US) (72, 75) STAUB, Ralf [DE/DE]; Ludwig Jahn Str. 4, 01109 Dresden (DE). AMON, Jürgen [DE/DE]; Stendaler Str. 15, 01109 Dresden (DE). URBANSKY, Norbert [DE/DE]; Dahlienweg 8, 01159 Dresden (DE). (74) W ILHELM, Jürgen et al. / etc.; Wilhelm & Beck, Nymphenburger Str. München (DE). (81) JP KR US. 139, 80636 (84)EP(ATBECHCYDEDKESFIFRGBGR IE IT LU MC NL PT SE TR). (51) 7 H01L 23/473 (11) WO 02/086968 (13) A2 (21) PCT/US02/12028 (22) 17 Apr/avr 2002 (17.04.2002) (25) en (26) en (30) 09/840,058 24 Apr/avr 2001 (24.04.2001) US (43) 31 Oct/oct 2002 (31.10.2002) (54) LIQUID-COOLED POWER SEMICON- DUCTOR DEVICE HEATSINK DISSIPATEUR DE CHALEUR POUR UN DISPOSITIF SEMI-CONDUCTEUR DE PUISSANCE REFROIDI PAR DU LIQUIDE (71) YORK INTERNATIONAL CORPORA- TION [US/US]; 631 South Richland Avenue, York, PA 17403 (US). (72) ROY, Steven; 1960 Manor Road, York, PA 17406 (US). JUDGE, John; 18599 Ridge Meadow Road, Stewartstown, PA 17363 (US). SCHNETZKA, Harold; 280 Estate Drive, York, PA 17404 (US). (74) SATTIZAHN, Brian; McNees Wallace & Nurick LLC, P.O. Box 1166, 100 Pine Street, Harrisburg, PA 17108-1166 (US). (81) AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK

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